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smsc EMC6D100/emc6d 101 page 1 rev. 09-09-04 datasheet EMC6D100/emc6d101* environmental monitoring and control device with automatic fan capability *note: the emc6d101 is not recommended for new designs. the emc6d102 fan control device with hardware monitoring and acoustic noise reduction features is the replacement device recommended for new designs. the EMC6D100 & emc6d101 monitor external voltages, temperatures, and fan speeds. they use this monitoring capability to alert the system to out of limit conditions and can automatically co ntrol the speeds of multiple fans in a pc or embedded system. the emc6d101, available in a 24-pin ssop package, and the EMC6D100, available in a 28-pin ssop package, are designed to be register compatib le. the EMC6D100 offers all the features of the emc6d101 plus additional voltage monitoring and system control features. the following is a summary of the features offered in both packages: product features ? 3.3 volt operation (5 vo lt tolerant input buffers) ? smbus 2.0 compliant interface ? fan control ? pwm (pulse width modulation) outputs (3) ? fan tachometer inputs (4) ? programmable automatic fan control based on temperature ? temperature monitor ? monitoring of two remote thermal diodes ? (+/- 3 deg. c accuracy) ? internal ambient temperature measurement ? limit comparison of all monitored values ? interrupt pin for out-of-limit temperature indication (EMC6D100 only) ? configurable offset for internal or external temperature channels ? voltage monitor ? monitor power supplies (+2.5v, +5v, +12v, vccp, and vcc) ? EMC6D100 monitors additional power supplies (+3.3v, +1.5v, +1.8v) ? limit comparison of all monitored values ? interrupt pin for out-of-limit voltage indication (EMC6D100 only) ? 5 vid (voltage identification) inputs ? xnor tree test mode ? mechanical packages ? 24 pin ssop package (emc6d101) ? 28 pin ssop package (EMC6D100) ordering information order number(s): emc61d100-dk for 28 pin ssop package emc61d101-ck for 24 pin ssop package
environmental monitoring and control device datasheet smsc EMC6D100/emc6d 101 page 2 rev. 09-09-04 datasheet 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? smsc 2004. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for c onstruction purposes is not necessarily given. although the information has been checked and is bel ieved to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain the la test specifications before placi ng your product order. the provisi on of this information does not convey to the purchaser of the described semiconductor devic es any licenses under any patent ri ghts or other intellectual p roperty rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (t he "terms of sale agreement"). the product may contain design def ects or errors known as anomalies which may caus e the product's functions to deviate from publis hed specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where produc t failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at t he risk of the customer. copies of this do cument or other smsc literature, as wel l as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www .smsc.com. smsc is a registered trademark of standard micros ystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and a ll warranties, including without limitation any and all implied warranties of merchantability, fitn ess for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usage of trade. in no event shall smsc be liable for an y direct, incidental , indirect, special, punitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of th e form of action, whether based on contract; tort; negligence of smsc or others; strict li ability; breach of warranty; or otherwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whet her or not smsc has been advised of the possibility of such damages.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d 101 page 3 rev. 09-09-04 datasheet EMC6D100/101 revisions page(s) section/figure/entry correction date revised cover note added advising of replacement of emc6d101 with emc6d102 as recommended device for new designs. 09/09/04 68 9.2 ratings for operation vcc supply current, max sleep mode changed from 300 to 500 01/07/03 21 6.3 monitoring modes updated temperature conversion values: changed 2.133ms to 2ms changed 1.511ms to 1.5ms updated total times: option 1 ? changed 362.616ms to 624 ms option 2 - changed 45.327ms to 78ms (see italicized text) 04/04/02 22 6.3.1 continuous monitoring mode updated values: changed 362.616ms to 624 ms (see italicized text) 04/04/02 68 9.2 ratings for operation updated typical values for the conversion time: option 1 - changed from 363 to 624 option 2 - changed from 45 to 78 modified note 3 to reflect these value changes. (see italicized text) 04/04/02 73 11.1 24 pin ssop package outline, 0.150? wide body, 0.025? pitch updated package outline. 04/04/02 74 11.2 28 pin ssop package outline, 0.150? wide body, 0.025? pitch updated package outline. 04/04/02 9 general description reference to ?d ual footprint? removed. 11/19/01 10 emc6d101 reference to ?dual footprint? removed. 11/19/01
environmental monitoring and control device datasheet smsc EMC6D100/emc6d 101 page 4 rev. 09-09-04 datasheet table of contents EMC6D100/101 revisions ......................................................................................................... ............... 3 chapter 1 general des cription................................................................................................. 9 chapter 2 pin configur ations .................................................................................................. 10 2.1 emc6d101....................................................................................................................... .............. 10 2.2 EMC6D100....................................................................................................................... .............. 11 chapter 3 recommended impl ementati on............................................................................ 12 chapter 4 pin descri ption........................................................................................................... 14 4.1 3.3v o peration , 5v t olerance .................................................................................................... 15 chapter 5 smbus inte rface ........................................................................................................ 16 5.1 s lave a ddress .............................................................................................................................. 1 6 5.2 smb us s lave i nterface ............................................................................................................... 16 5.3 b us p rotocols ............................................................................................................................. 17 5.3.1 byte protocols................................................................................................................. ......... 17 5.4 i nvalid p rotocol r esponse b ehavior ......................................................................................... 18 5.4.1 undefined re gisters ............................................................................................................ .... 19 5.5 g eneral c all a ddress r esponse ................................................................................................ 19 5.6 s lave d evice t ime -o ut ................................................................................................................. 19 5.7 s tretching the sclk s ignal ....................................................................................................... 19 5.8 smb us t iming ............................................................................................................................... .19 5.9 b us r eset s equence .................................................................................................................... 19 5.10 smb us a lert r esponse a ddress ............................................................................................. 19 chapter 6 hardware monitoring ............................................................................................ 21 6.1 i nput m onitoring .......................................................................................................................... 21 6.2 r esetting the h ardware m onitoring b lock .............................................................................. 21 6.2.1 power on reset ................................................................................................................. ..... 21 6.2.2 soft reset (initialization).................................................................................................... ...... 21 6.3 m onitoring m odes ........................................................................................................................ 21 6.3.1 continuous moni toring mode................................................................................................... 22 6.3.2 cycle monito ring m ode.......................................................................................................... .. 22 6.4 i nterrupt s tatus r egisters ........................................................................................................ 23 6.4.1 diode f ault .................................................................................................................... .......... 24 6.5 i nterrupt p in ............................................................................................................................... .24 6.6 l ow p ower m odes ........................................................................................................................ 25 6.6.1 sleep mo de..................................................................................................................... ......... 25 6.6.2 shutdown mode.................................................................................................................. ..... 26 6.7 a nalog v oltage m easurement .................................................................................................... 26 6.8 v oltage id............................................................................................................................. ........ 26 6.9 t emperature m easurement ......................................................................................................... 26 6.9.1 internal temperat ure measurement........................................................................................ 26 6.9.2 external temperat ure measurement....................................................................................... 27 6.9.3 temperature da ta format ....................................................................................................... 2 7 6.9.4 offset r egister................................................................................................................ ......... 28 6.9.5 second offset register ......................................................................................................... .. 28 6.10 t emperature s moothing ........................................................................................................... 28 chapter 7 fan cont rol ................................................................................................................ 29 7.1 g eneral d escription .................................................................................................................... 29
environmental monitoring and control device datasheet smsc EMC6D100/emc6d 101 page 5 rev. 09-09-04 datasheet 7.2 l imit and c onfiguration r egisters ............................................................................................. 29 7.3 d evice s et -u p ............................................................................................................................... 30 7.4 pwm f an s peed c ontrol ............................................................................................................. 30 7.4.1 manual fan control operating mode ...................................................................................... 30 7.4.2 auto fan control operating mode .......................................................................................... 31 7.4.3 spin up ........................................................................................................................ ............ 34 7.4.4 hottest option................................................................................................................. ......... 35 7.5 f an s peed m onitoring .................................................................................................................. 35 7.5.1 fan tachomet er i nputs .......................................................................................................... .35 7.5.2 detection of a stalled fan ..................................................................................................... .. 36 7.5.3 fan interrupt status bits...................................................................................................... .... 36 7.6 l inking f an t achometers to pwm s ............................................................................................ 36 7.7 s ystem s ynchronization .............................................................................................................. 36 chapter 8 register set................................................................................................................ 37 8.1 u ndefined r egisters .................................................................................................................... 40 8.2 r egister 10 h : smsc t est r egister ............................................................................................ 40 8.3 r egister 1e, 1f h : o ffset r egisters ........................................................................................... 40 8.4 r egisters 20-24 h , 70-72 h : v oltage r eading .............................................................................. 40 8.5 r egisters 25-27 h : t emperature r eading ................................................................................... 41 8.6 r egisters 28-2f h : f an t achometer r eading .............................................................................. 42 8.7 r egisters 30-32 h : c urrent pwm d uty ....................................................................................... 42 8.7.1 manual mode .................................................................................................................... ....... 43 8.8 r egister 3e h : c ompany id ........................................................................................................... 44 8.9 r egister 3f h : v ersion / s tepping ................................................................................................ 44 8.10 r egister 40 h : r eady /l ock /s tart m onitoring ........................................................................ 44 8.11 r egister 41 h : i nterrupt s tatus r egister 1............................................................................ 46 8.12 r egister 42 h : i nterrupt s tatus r egister 2............................................................................ 47 8.13 r egister 7d h : i nterrupt s tatus r egister 3 ........................................................................... 48 8.14 r egister 43 h : vid ...................................................................................................................... 48 8.15 r egisters 44-4d h , 73-78 h : v oltage l imit r egisters .............................................................. 49 8.16 r egisters 4e-53 h : t emperature l imit r egisters ................................................................... 50 8.17 r egisters 54-5b h : f an t achometer l ow l imit ........................................................................ 51 8.18 r egisters 5c-5e h : f an c onfiguration .................................................................................... 51 8.18.1 bits [7:5] zone/m ode ........................................................................................................... .51 8.18.2 bit [4] pw m invert ............................................................................................................. ... 52 8.18.3 bit [3] reserved............................................................................................................... ..... 52 8.18.4 bits [2:0] spin up............................................................................................................. ..... 52 8.19 r egisters 5f-61 h : a uto f an s peed r ange , pwm f requency ................................................ 53 8.20 r egister 62 h , 63 h : m in /o ff , s pike s moothing ......................................................................... 55 8.21 r egisters 64-66 h : m inimum pwm d uty c ycle ......................................................................... 56 8.22 r egisters 67-69 h : t emperature limit .................................................................................... 57 8.23 r egisters 6a-6c h : a bsolute t emperature l imit .................................................................... 57 8.24 r egisters 6d-6e h : z one hysteresis r egisters .................................................................. 58 8.25 r egister 6f: xor t est r egister ............................................................................................. 59 8.26 r egister 79 h : t est m ode r egister .......................................................................................... 59 8.27 r egister 7a h : e rror d ebug r egister ..................................................................................... 60 8.28 r egister 7b h : t est d igital v alue r egister ............................................................................ 61 8.29 r egister 7c h : s pecial f unction r egister .............................................................................. 61 8.30 r egister 7e h : i nterrupt e nable r egister .............................................................................. 62 8.31 r egister 7f h : c onfiguration r egister ................................................................................... 63 8.32 r egister 80 h : f an t emp i nterrupt e nable r egister .............................................................. 64 8.33 r egister 81 h : tach_pwm r egister ....................................................................................... 65 8.34 r egister 83 h : s ync p ulse c onfiguration register: on/off ............................................ 66 8.34.1 bit [4] on ..................................................................................................................... ......... 66 8.35 r egisters 86-88 h : s mooth t emperature r eading r egisters ................................................ 66
environmental monitoring and control device datasheet smsc EMC6D100/emc6d 101 page 6 rev. 09-09-04 datasheet 8.36 r egister 89 h : adc2 lsb t est .................................................................................................. 67 8.37 r egisters 8a-8d h : input test r egister ................................................................................... 67 8.38 r egisters 8e-91 h : out put test r egister ............................................................................... 67 8.39 r egisters 8a-8d h : input test r egister ................................................................................... 67 8.40 r egisters 8e-91 h : out put test r egister ............................................................................... 67 chapter 9 operational de scription ...................................................................................... 68 9.1 m aximum g uaranteed r atings ..................................................................................................... 68 9.2 r atings for o peration ................................................................................................................. 68 chapter 10 timing di agrams ........................................................................................................ 71 10.1 pwm o utputs ............................................................................................................................ 71 10.1.1 with synchronization........................................................................................................... .71 10.1.2 without synchr onizati on....................................................................................................... 7 1 10.2 s m b us i nterface ....................................................................................................................... 72 chapter 11 package outlines .................................................................................................... 73 11.1 24 p in ssop p ackage o utline , 0.150? w ide b ody , 0.025? p itch ............................................ 73 11.2 28 p in ssop p ackage o utline , 0.150? w ide b ody , 0.025? p itch ............................................. 74 chapter 12 appendix b ? adc volt age conver sion............................................................ 75
environmental monitoring and control device datasheet smsc EMC6D100/emc6d 101 page 7 rev. 09-09-04 datasheet list of figures figure 2.1 ? pin configu ration for emc6d1 01.................................................................................... .........10 figure 2.2 ? pin configu ration for emc6d1 00.................................................................................... .........11 figure 3.1 - fan drive circuitry (app ly to pwm driving two fa ns).....................................................12 figure 3.2 - fan drive circuitry (app ly to pwm drivi ng one fan)........................................................12 figure 3.3 - fan tachometer ci rcuitry (apply to each fa n).................................................................13 figure 3.4 - remote diode (apply to remo te2 li nes) ............................................................................. ...13 figure 5.1 - address selection on EMC6D100/ emc6d1 01...........................................................................1 6 figure 6.1 - interrupt and interrup t status registe r contro l .......................................................24 figure 7.1 - automatic fa n control flow diagram................................................................................ ..32 figure 7.2 - automa tic fan co ntrol............................................................................................. ..................34 figure 7.3 - fan tachomete r input and cl ock so urce ........................................................................... 35 figure 8.1 - fan activity above fan te mp limit................................................................................. ...........53 figure 8.2 - what EMC6D100/emc6d101 sees with and withou t spike smoot hing............................55 figure 10.1 - pwmx outp ut timing, sync_msk=0 ................................................................................... .......71 figure 10.2 - pwmx outp ut timing, sync_msk=1 ................................................................................... .......71 figure 10.3 ? smbus ti ming..................................................................................................... ..............................72
environmental monitoring and control device datasheet smsc EMC6D100/emc6d 101 page 8 rev. 09-09-04 datasheet list of tables table 5.1 -smbus wr ite byte protoc ol........................................................................................... ..............................17 table 5.2 - smbus re ad byte protocol........................................................................................... .............................18 table 5.3 - smbus s end byte pr otocol........................................................................................... .............................18 table 5.4 - smbus rece ive byte protocol ........................................................................................ ...........................18 table 5.5 - modified smbus receive byte protocol re sponse to ara ............................................................... ........20 table 8.1 - voltage vs. register reading....................................................................................... ..............................41 table 8.2 - temperature vs. register reading ................................................................................... .........................42 table 8.3 - pwm duty vs. register reading...................................................................................... ..........................43 table 8.4 ? voltage limits vs. regist er setting................................................................................ ............................49 table 8.5 - temperature li mits vs regist er se ttings ............................................................................ .......................50 table 8.6 - f an zone se tting ................................................................................................... ....................................52 table 8.7 - fan sp in-up register............................................................................................... ..................................53 table 8.8 - register setting vs. pw m frequenc y ................................................................................. .......................54 table 8.9 - register setti ng vs. temperat ure range ............................................................................. ......................54 table 8.10 - spik e smoothing ................................................................................................... ...................................56 table 8.11 - pwm output below li mit depending on value of off/min.............................................................. ........56 table 8.12 - pwm duty vs. register setting ..................................................................................... ...........................56 table 8.13 - temperature li mit vs. regist er se tting ............................................................................ ........................57 table 8.14 - absolute limi t vs. register setting ............................................................................... ...........................58 table 8.15 - hyster esis settings ............................................................................................... ...................................59 table 10.1 - timing fo r pwm[1:3] outputs....................................................................................... .............................71 table 12.1 ? analog-to-digital volt age conversions for hardwa re monitori ng bloc k...................................................75
environmental monitoring and control device datasheet smsc EMC6D100/emc6d 101 page 9 rev. 09-09-04 datasheet chapter 1 general description the EMC6D100 & emc6d101 are environmental monito ring and control devices with automatic fan control capability for pcs and embedded systems. these acpi compliant devices provide hardware monitoring for up to eight voltages and three thermal zones, measure the speed of up to four fans, and control the speed of multiple dc fans using three pulse width modulators (pwm). note that it is possible to control more than three fans by connecting two fans to one pwm output. the emc6d101 is available in a 24-pin ssop pack age and the EMC6D100 is available in a 28-pin ssop package. these devices are designed to be register co mpatible. the EMC6D100 offers all the features of the emc6d101 plus additional voltage monitoring and system control features. the EMC6D100 & emc6d101 hardware monitoring provides analog inputs for monitoring external voltages of +2.5v, +5v, +12v and vccp. these device s have the capability to monitor their own internal vcc or vsb. in addition to monitoring the processor voltage, vid inputs are available to identify the voltage specification. the emc6d1 00 has the added functionality of monitoring +3.3v, +1.5v and +1.8v. external components are not required for voltage scaling or similar treatment. these devices include support for monitoring three thermal zones: two external and one internal. the external temperatures are measured via thermal diode inputs capable of monitoring remote devices. in addition, they are equipped with an ambient temperat ure sensor for measuring the internal temperature. pulse width modulators (pwm) control the speed of the fans by varying the output duty cycle of the pwm. the speed of each fan is monitored by a fan tachometer input. the measured values are compared to values stored in limit registers to det ect if a fan has stalled or seized. fan speed may be under host software control or au tomatic control of the EMC6D100 & emc6d101. in host control mode, the host software continuously mo nitors temperature and fan speed registers, makes decisions as to desired fan speed and sets the pw m?s to drive the required fan speed. the EMC6D100 has an interrupt pin (int#), which may be used to inte rrupt the host on out-of-lim it temperature or voltage condition enabling an acpi response as opposed to the host software continuously monitoring status. in auto ?zone? mode, the EMC6D100 & emc6d101 logic c ontinuously monitors the temperature and fan speeds and adjusts speeds without intervention from the host cpu. fan speed is adjusted according to an algorithm using the temperature measured in the sele cted zone, the high and low limits set by the user, and the current fan speed. the EMC6D100 & emc6d101 registers are accessibl e through the smbus inte rface in both ?standby mode? and ?active mode?.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 10 rev. 09-09-04 datasheet chapter 2 pin configurations the environmental monitoring and control device (emc) is offered in two packages: the emc6d101, which is a 24 pin ssop, and the em c6d100, which is a 28 pin ssop. 2.1 emc6d101 the emc6d101 is a 24 pin ssop. 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 sda scl gnd vcc vid0 vid1 vid2 vid3 vid4 tach3 pwm2 tach1 tach2 pwm1/xtest out vccp 2.5v 12v 5v remote1+ remote1- remote2+ remote2- tach4/address select pwm3/address enable emc6d101 figure 2.1 ? pin conf iguration for emc6d101
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 11 rev. 09-09-04 datasheet 2.2 EMC6D100 the EMC6D100 is a 28 pin ssop. the functions that th is chip supports in addition to the emc6d101 are listed below. additional features offered in EMC6D100: ? voltage monitoring for +3.3v, +1.5v, +1.8v inputs ? interrupt pin 8 7 6 5 4 3 2 1 22 23 21 24 25 26 27 28 14 13 12 11 10 9 15 16 17 18 19 20 sdat sclk vss vcc vid0 vid1 vid2 vid3 (1) int# (1) 1.8v_in tach3 pwm2 tach1 tach2 pwm1/xtestout vccp_in +2.5v_in +12v_in +5v_in +3.3v_in (1) +1.5v_in (1) vid4 remote1+ remote1- remote2+ remote2- tach4/address select pwm3 /address enable (1) fan control signal differs from emc6d101 EMC6D100 figure 2.2 ? pin conf iguration for EMC6D100
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 12 rev. 09-09-04 datasheet chapter 3 recommended implementation the following figures show the recommended circui try on the board for the pwm outputs, tachometer inputs, and remote diodes. figure 3.1 shows how th e part can be used to control additional fans by connecting two fans to one pwm output. mmbt3904 mmbt2222 mmbt2222 10 10 2.2k 1k 3.3v 3.3v fan1 fan2 m m 12v pwm3 empty empty figure 3.1 - fan drive circuitry (a pply to pwm driving two fans) mmbt2222 0 470 3.3v fan m 12v pwmx empty figure 3.2 - fan drive circuitry (a pply to pwm driving one fan)
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 13 rev. 09-09-04 datasheet 10k 10k 12v tach output from fan 4.7k tach input figure 3.3 - fan tachometer circuitry (apply to each fan) out out remote2- remote2+ 100pf 5% 100v npo 603 1 2 2 3 mmbt3904 xstr 1 figure 3.4 - remote diode (apply to remote2 lines) notes: ? 100pf cap is optional and should be placed close to the EMC6D100/emc6d101 if used. ? the voltage at pwm3 must be at least 2. 0v to avoid triggering address enable.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 14 rev. 09-09-04 datasheet chapter 4 pin description symbol pin (emc6d101) pin (EMC6D100) type name and function sda 1 1 digital i/o (open drain) system management bus data. open-drain output. 5v tolerant. smbus 2.0 compliant. smbus scl 2 2 digital i/o (open drain) system management bus clock. open-drain output. 5v tolerant. smbus 2.0 compliant. vid0 5 5 digital input voltage identification signal from the processor. this value is read in the vid0- vid4 status regist er. input only. vid1 6 6 digital input voltage identification signal from the processor. this value is read in the vid0- vid4 status regist er. input only. vid2 7 7 digital input voltage identification signal from the processor. this value is read in the vid0- vid4 status regist er. input only. vid3 8 8 digital input voltage identification signal from the processor. this value is read in the vid0- vid4 status regist er. input only. processor vid lines vid4 19 21 digital input voltage identification signal from the processor. this value is read in the vid0- vid4 status regist er. input only. vss 3 3 ground ground for all analog and digital circuitry. power vcc 4 4 power positive power supply. nominal 3.3v. vcc is monitored by the hardware monitoring block. [can be powered by +3.3v standby power if monitoring in low power states is required.] +5v 20 24 analog input analog input for +5v monitoring. +2.5v 22 26 analog input analog input for +2.5v monitoring. vccp 23 27 analog input analog input for +vccp (processor voltage) monitoring. +12v 21 25 analog input analog input for +12v monitoring. +1.5v (note 1) - 22 analog input analog input for +1.5v monitoring. +1.8v (note 1) - 10 analog input analog input for +1.8v monitoring. voltage monitoring +3.3v (note 1) - 23 analog input analog input for +3.3v monitoring.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 15 rev. 09-09-04 datasheet symbol pin (emc6d101) pin (EMC6D100) type name and function remote1- 17 19 remote thermal diode negative input negative input (current sink) from the first remote thermal diode. remote1+ 18 20 remote thermal diode positive input positive input (current source) from the first remote thermal diode. remote2- 15 17 remote thermal diode negative input negative input (current sink) from the second remote thermal diode. temperature monitoring remote2+ 16 18 remote thermal diode positive input positive input (curr ent source) from the second remote thermal diode. tach1 11 13 digital input input for monitoring tachometer of fan 1 tach2 12 14 digital input input for monitoring tachometer of fan 2 tach3 9 11 digital input input for monitoring tachometer of fan 3 fan tachometer tach4/ address select 14 16 digital input input for monitoring tachometer of fan 4. if in address select mode, determines the smbus address of the device. pwm1/xtest out 24 28 digital open drain output pwm output 1 controlling speed of fan. when in xnor tree test mode, functions as xnor tree output. pwm2 10 12 digital open drain output pwm output 2 controll ing speed of fan. pwm3/addre ss enable# 13 15 digital open drain output pwm output 3 controll ing speed of fan. note: if pulled to ground at power on, enables address select mode (address select pin controls smbus address of the device). fan control int# (note 1) - 9 digital open drain output interrupt output. note 1: these pins are in EMC6D100 only. 4.1 3.3v operation, 5v tolerance the EMC6D100/emc6d101 is intended to operate with a nominal 3.3v power supply. the analog voltage pins are connected to voltage sources at their respec tive nominal levels. all digital signal pins are 3v switching but are tolerant to 5v.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 16 rev. 09-09-04 datasheet chapter 5 smbus interface the host processor communicates with the environment al monitoring and control device (emc), through a series of read/write registers, via the smbus interfac e. smbus is a serial communication protocol between a computer host and its peripheral devices. 5.1 slave address the default slave address is 0101110b. if this addr ess is desired, the designer should not ground the address enable# pin and should not apply a st rapping resistor to the address select pin. if multiple devices are implemented in a system or another smbus device requires address 0101110b, tach4 and pwm3 must be disabled. in this case, addressing is implemented as follows: the board designer will apply a 10k ? pull-down resistor to ground on the address enable# pin. upon power up, the EMC6D100/emc6d101 device will be plac ed into address enable mode and assign itself an smbus address according to the address select input. the device will latch the address during the first valid smbus transaction in which the first five bits of the targeted addr ess match those of the EMC6D100/emc6d101 address. this feat ure eliminates the possibility of a glitch on the smbus interfering with address selection. address select board implementation smbus address 0 pulled to ground through a 10k ? resistor 0101100b 1 pulled to 3.3v through a 10k ? resistor 0101101b in this way, there can be up to three EMC6D100/e mc6d101 devices on the smbus at any time. multiple EMC6D100/emc6d101 devices can be used to monito r additional processors and temperature zones. start sda scl address decided first five address bits 0 1 0 1 1 figure 5.1 - address select ion on EMC6D100/emc6d101 5.2 smbus slave interface the EMC6D100/emc6d101 device smbus implementation is a subset of the smbus interface to the host. the device is a slave-only smbus device. the implementation in the device is a subset of smbus since it only supports four protocols.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 17 rev. 09-09-04 datasheet the write byte, read byte, send byte, and receive byte protocols are the only valid smbus protocols for the device. this part responds to other protocols as described in the invalid protocol section. reference the system management bus specification, rev 2.0. the smbus interface is used to read and write the registers in the device. the register set is shown in section chapter 8 register set on page 37. 5.3 bus protocols typical write byte, read byte, send byte, and receive byte protocols are shown below. register accesses are performed using 7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. the shading indicates the emc device is driv ing data on the sda line; otherwise, host data is on the sda line. the slave address is the unique smbus interface address for the emc device that identifies it on smbus. the register address field is the internal address of t he register to be accessed. the register data field is the data that the host is attempting to write to the register or the contents of the register that the host is attempting to read. note: data bytes are transferred msb first. 5.3.1 byte protocols when using the emc smbus interface for byte transfers, a write will always consist of the smbus interface address byte, followed by the internal addr ess register byte, then the data byte. there are two cases for a read: 1. the normal read protocol consists of a write to the emc device with the smbus interface address byte, followed by the internal address register byte. then restart the serial communication with a read consisting of the smbus interface address byte , followed by the data byte read from the emc device. this can be accomplished by using the read byte protocol or by using the send byte protocol followed by the receive byte protocol. 2. if the internal address register is known to be at the desired address, simp ly read the emc register with the smbus interface address byte , followed by the data byte read from the emc register block. this corresponds to the receive byte protocol. write byte the write byte protocol is used to write data to the regi sters. the data will only be written if the protocol shown in table 5.1 is performed correctly. only one by te is transferred at time for a write byte protocol. table 5.1 -smbus write byte protocol field: start slave addr wr ack reg. addr ack reg. data ack stop bits: 1 7 1 1 8 1 8 1 1 read byte the read byte protocol is used to read data from the registers. the data will only be read if the protocol shown in table 5.2 is performed correctly. only one by te is transferred at time for a read byte protocol.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 18 rev. 09-09-04 datasheet table 5.2 - smbus read byte protocol field: start slave addr wr ack reg. addr ack start slave addr rd ack reg. data nack stop bits: 1 7 1 1 8 1 1 7 1 1 8 1 1 send byte the send byte protocol is used to set the internal ad dress register to the correct register in the emc register block. no data is transferred for a send byte protocol. the send byte can be followed by the receive byte protocol described below in order to read data from the register. the send byte protocol cannot be used to write data - if data is to be written to a register then th e write byte protocol must be used as described in subsection above. the send by te protocol is shown in the table below. table 5.3 - smbus send byte protocol field: start slave addr wr ack reg. addr ack stop bits: 1 7 1 1 8 1 1 receive byte the receive byte protocol is used to read data from the registers when the register address is known to be at the desired address (using the internal address re gister). this is used when the register address has been written to the desired address using the se nd byte protocol. this can be used for successive reads of the same register. the data will only be re ad if the protocol shown in table 5.4 is performed correctly. only one byte is transferred at time for a receive byte protocol. table 5.4 - smbus receive byte protocol field: start slave addr rd ack reg. data nack stop bits: 1 7 1 1 8 1 1 5.4 invalid protocol response behavior registers that are accessed with an invalid protocol will not be updated. a register will only be updated following a valid protocol. the only valid protocols are the write byte, read byte, send byte, and receive byte protocols, which are described above. the EMC6D100/emc6d101 device responds to three smbus slave addresses: 1) the smbus slave address that supports the va lid protocols defined in the previous sections is determined by the level on the address se lect and address enable pins as shown in section 5.1 slave address on page 16. 2) smbus general call address (0001 100). t he smbus will only respond to the general call address if the smbus alert response interrupt was generated to request a response from the host. the smbus allert response is de fined in section 5.10 smbus alert response address on page 19. attempting to communicate with the emc device over t he smbus with an invalid slave address, or invalid protocol will result in no response, and the smbus slave interface will return to the idle state.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 19 rev. 09-09-04 datasheet the only valid registers that are accessible by the sm bus slave address are the registers defined in the registers section. see section below for response to undefined registers. 5.4.1 undefined registers reads to undefined registers return 00h. writes to und efined registers have no effect and return no error. 5.5 general call address response the emc device will not respond to a general call address of 0000_000. 5.6 slave device time-out according to smbus specification, v2.0 devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds 25ms (t timeout, min ). devices that have detected this condition must reset their communication and be able to receive a new start condition no later than 35ms (t timeout, max ). note: some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or stop condition 5.7 stretching the sclk signal the emc device supports stretching of the sclk by other devices on the smbus. the emc device does not stretch the sclk. 5.8 smbus timing the smbus slave interface complies with the smbus ac timing specification. see the smbus timing in the ?timing diagram? section. 5.9 bus reset sequence the smbus slave interface will reset and return to the idle state upon a start field followed immediately by a stop field. 5.10 smbus alert response address EMC6D100: the EMC6D100 device implements the smbalert# signal. the int# interrupt pin can be used as the smbalert#. smbalert# is used in conjunction with the smbus general call address, 0001 100. in order for the int# signal to become active and for the device to respond to the alert response address, the inten bit (register 7ch bit 2) must be set and the event must be properly enabled onto the int# pin. each interrupt event must be enabled into the interr upt status registers, and t he status bits must be
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 20 rev. 09-09-04 datasheet enabled onto the int# pin via the enable bits for each ty pe of event (i.e., temperat ure, voltage and fan). see the ?interrupt status register? section. the device can signal the host that it wants to talk by pulling the smbalert# low, if a status bit is set in one of the interrupt status regist ers and properly enabled onto the int# pin. the host processes the interrupt and simultaneously accesses all smbalert# devices through a modified receive byte operation with the alert response address (ara). the EMC6D100/emc6d101 device, which pulled smbalert# low, will acknowledge the alert response address and respond with its device address. the host performs a modified receive byte operation wi th the alert response address. the 7-bit device address provided by the EMC6D100/emc6d101 device is plac ed in the 7 most significant bits of the byte. the eighth bit can be a zero or one. table 5.5 - modified smbus receive byte protocol response to ara field: start alert response address rd ack EMC6D100/emc6d101 slave address nack stop bits: 1 7 1 1 8 1 1 after acknowledging the slave address, the EMC6D100/emc6d101 device will disengage the smbalert# pulldown by clearing the int enable bit. if t he condition that caused the interrupt remains, the fan control device will reassert the smbalert# on the next monitoring cycle, provided the int enable bit has been set back to ?1? by software. emc6d101: the emc6d101 part does not have an interrupt pin. this part does not normally acknowledge or respond to the alert response address. however, the device will respond as described above if the inten bit (register 7ch bit 2) is set, and if a status bit is set in one of the interrupt status registers and is properly enabled onto the int# signal. each interrupt event must be enabled into the interr upt status registers, and the status bits must be enabled ont o the int# signal via the enable bits for each type of event (i.e., temperature, voltage and fan). see t he ?interrupt status register? section.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 21 rev. 09-09-04 datasheet chapter 6 hardware monitoring the following sub-sections describe the hardware monitoring block. 6.1 input monitoring the EMC6D100/emc6d101 device?s monitoring function is started by writing a ?1? to the start bit in the ready/lock/start register (0x40). measured values from the analog inputs and temperature sensors are stored in reading registers. the values in the readi ng registers can be accessed via the smbus interface. these values are compared to the programmed limits in the limit register. the out-of-limit and diode fault conditions are stored in the interrupt status registers. note: all limit and parameter registers must be set before the start bit is set to ?1?. once the start bit is set, these registers become read-only. 6.2 resetting the hardware monitoring block 6.2.1 power on reset all the registers in the hardware monitor block, except the reading registers, reset to a default value when power is applied to the block. the default state of the register is shown in the table in the register summary subsection. the default state of reading re gisters are not shown because these registers have indeterminate power on values. note: usually the first action after power up is to write limits into the limit registers. 6.2.2 soft reset (initialization) setting bit 7 of the conf register performs a soft reset. this bit is self-clearing. soft reset performs reset on all the registers except the reading registers. 6.3 monitoring modes the hardware monitor block supports two monitoring modes: continuous mode and cycle mode. these modes are selected using bit 1 of the special function register (7ch). the following subsections contain a description of these monitoring modes. for each mode, there are two options for the number of measurements that are performed on each temperature and voltage reading. these options are selected using bit 5 of the special function register (7ch). these options are as follows: 1. 128 measurements are averaged for the remote dio de temperature reading and 8 measurements are averaged for all voltage and the internal temperature reading.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 22 rev. 09-09-04 datasheet 2. 16 measurements are averaged for the remote diode tem perature reading and a single measurement is taken for all voltage and the internal temperature reading (i.e., no averaging). this is a power saving option. this is the default operation. for option 1, the block performs a total of (2 x 128) + (1 x 8) + (8 x 8) = 328 conversions. option 2 reduces the number of conversions to (2 x 16) + (1 x 1) + (8 x 1) = 41. each temperature conversion takes 2 ms approx. and each voltage conversion takes 1.5 ms approx. the total time for option 1 (328 conversions) is (2x128x2) + (1x8x2) + (8x8x1.5) = 624 ms. the total time for option 2 (41 conversions) is (2x16x2) + (1x1x2) + (8x1x1.5) = 78 ms. 6.3.1 continuous monitoring mode in the continuous monitoring mode, the sampling and conversion process is performed continuously for each voltage and temperature reading after the start bit is set high. the time for each voltage and temperature reading is shown above for each measurement option. the continuous monitoring function is started by doing a write to the ready/lock/st art register, setting the start bit (bit 0) high. the part then performs a ?round robin? sampling of the inputs, in the order shown below (corresponding to locations in the ram). sampling of all values occurs in 624 ms (or 78 ms - see above). sampling order register 1 remote diode temp reading 1 2 ambient temperature reading 3 vcc reading 4 +12v reading 5 +5v reading 6 +3.3v reading 7 +2.5v reading 8 vccp (processor) reading 9 remote diode temp reading 2 10 +1.8v reading 11 +1.5v reading when the continuous monitoring functi on is started, it cycles through ea ch measurement in sequence, and it continuously loops through the sequence approx imately once every 624 ms (or 78 ms ? see above). each measured value is compared to values stor ed in the limit registers. when the measured value violates (or is equal to) the programmed limit the ha rdware monitor block will set a corresponding status bit in the interrupt status registers. if auto fan option is selected, the hardware will adjust the operation of the fans accordingly. see section 7.4.2 auto fan control operating mode on page 31. the results of the sampling and conversions can be found in the reading registers and are available at any time. 6.3.2 cycle moni toring mode in cycle monitoring mode, the part completes all sampling and conversions, then waits to repeat the process. it repeats the sampling and conversion proce ss every second (1.4 sec max). the sampling and
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 23 rev. 09-09-04 datasheet conversion of each voltage and temper ature reading is performed once every monitoring cycle. this is a power saving mode. the cycle monitoring function is started by doing a wr ite to the ready/lock/start register, setting the start bit (bit 0) high. the part then performs a ?round robin? sampling of the inputs, in the order shown above. when the cycle monitoring function is started, it cycles through eac h measurement in sequence, and it performs a single conversion for each voltage and temperature approximately once every second. each measured value is compared to values stored in the li mit registers. when the measured value violates (or is equal to) the programmed limit the hardware monito r block will set a corresponding status bit in the interrupt status registers. if auto fan option is selected, the hardware will adjust the operation of the fans accordingly. see section 7.4.2 auto fan control operating mode on page 31. the results of each sampling and conversion can be fou nd in the reading registers and are available at any time, however, they are only updated once every 1-1.4 seconds. 6.4 interrupt status registers the hardware monitor block contains three interrupt st atus registers. these registers are used to reflect the state of all temperature, voltage and fan violation of limit error conditions and diode fault conditions that the hardware monitor block monitors. when an error occurs during the conversion cycle, its corresponding bit is set in its respective interrupt status register. the bit remains set until the register is read by software, at which time the bit will be cleared to ?0? if the associated error event no longer vi olates the limit conditions or if the diode fault condition no longer exists. reading the register will not cause a bit to be cleared if the source of the status bit remains active. these registers are read only ? a write to these regi sters have no effect. these registers default to 0x00 on vcc por and initialization. see the description of the inte rrupt status registers in se ction chapter 8 register set. each interrupt event can be enabled into the interrupt status registers. see the figure below for the status and enable bits used to control the interrupt bits and int# pin.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 24 rev. 09-09-04 datasheet int_sts1 reg fan_en (ftie[0]) 2.5v_error (int1[0]) vccp_error (int1[1]) vcc_error (int1[2]) 5v_error (int1[3]) zone 1 limit (int1[4]) zone 2 limit (int1[5]) zone 3 limit (int1[6]) int_sts2 reg 12v_error (int2[0]) fan1 stalled (int2[2]) fan2 stalled (int2[3]) fan3 stalled (int2[4]) fan4 stalled (int2[5]) diode 1 fault (int2[6]) diode 2 fault (int2[7]) int_sts3 reg 1.5v_error (int3[0]) 1.8v_error (int3[1]) 3.3v_error (int3[2]) + + int# 2.5v_error_en (inte[2]) vccp_error_en (inte[3]) vcc_error_en (inte[7]) 5v_error_en (inte[5]) diode 1_en (sftr[6]) diode 2_en (sftr[7]) 12v_error_en (inte[6]) fan1 stalled_en (ftie[1]) fan2 stalled_en (ftie[2]) fan3 stalled_en (ftie[3]) fan4 stalled_en (ftie[4]) diode 1_en (sftr[6]) diode 2_en (sftr[7]) 1.5v_error_en (inte[0]) 1.8v_error_en (inte[1]) 3.3v_error_en (inte[4]) voltage_en (sftr[3]) 2.5v_error vccp_error 3.3v_error 5v_error zone 1 limit zone 2 limit zone 3 limit 12v_error fan1 stalled fan2 stalled fan3 stalled fan4 stalled diode 1 fault diode 2 fault 1.5v_error 1.8v_error 3.3v_error int_en (sftr[2]) + temp_en (ftie[5]) + ambient_en (ftie[6]) figure 6.1 - interrupt and interrupt status register control 6.4.1 diode fault the EMC6D100/emc6d101 chip automatically sets the asso ciated diode fault bit to 1 when there is either a short or open circuit fault on the remote x+ or re mote x- thermal diode input pins. the occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding zone error bit to be set. this will cause the int# pin to become active if enabled. it will also cause the auto fan algorithm to turn any f ans associated with that zone on full when it sees a reading of 80h. if the diode is disabled, the fault bit in the interrupt status register will not be set. in this case, the occurrence of a fault will cause 00h to be loaded into the associated reading regi ster. the limits must be programmed accordingly to prevent unwanted fan spee d changes based on this temperature reading. if the diode is disabled and a fault condition does not exist on the diode pins, then the associated reading register will contain a ?valid? reading. 6.5 interrupt pin EMC6D100 only . the int# function is used as an interrupt output for out-of-limit temperature, voltage events, and/or fan errors.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 25 rev. 09-09-04 datasheet ? to enable the int# pin for the interrupt function, set bit 1 of the conf register (7fh) to ?1?. ? to enable the interrupt pin to go active, set bit 2 of the special function register (7ch) to ?1?. to enable temperature event, voltage events and/or fan events onto the int# pin: ? to enable out-of-limit temperature ev ents set bit 5 of the fan temp interrupt enable register (80h) to ?1?. ? to enable out-of-limit voltage events set bit 3 of the special function register (7ch) to ?1? ? to enable fan tachometer error events set bit 0 of the fan temp interrupt enable register (80h) to ?1?. see figure 6.1 above. the following description assu mes that the interrupt enable bits for all events are set to enable the interrupt status bits to be set. if the internal or remote temperature reading is not wi thin the low or high temperature limits, int# will be active low (if the temp_en bit is set). this pin will re main low while the internal temp error bit or one or both of the the remote temp error bits in interrupt status 1 register is set and the enable bit is set. the int# pin will not become active low as a result of the remote diode fault bits becoming set. however, the occurrence of a fault will cause 80h to be loaded in to the associated reading register, which will cause the corresponding zone error bit to be set. this will cause the int# pin to become active if enabled. the int# pin can be enabled to indicate out-of-limit vo ltages. bit 3 of the special function register (7ch) is used to enable this option. when this bit is set, if one or more of the voltage readings is not within the low or high limits, int# will be active low. this pin will remain low while the associated voltage error bit in the interrupt status register 1, interrupt status register 2 and interrupt status register 3 is set. the int# pin can be enabled to indicate fan errors. bit 0 of the fan temp interrupt enable register (80h) is used to enable this option. this pin will remain low wh ile the associated fan error bit in the interrupt status register 2 is set. the int# pin will remain low while any bit is set in any of the interrupt status registers. reading the interrupt status registers will cause the logic to attempt to clear the status bits; ho wever, the status bits will not clear if the interrupt stimulus is still active. t he interrupt enable bit (special function register bit[2]) should be cleared by software before reading the interrupt status registers to insure that the int# pin will be re-asserted while an interrupt event is active, wh en the int_en bit is written to ?1? again. the int# pin can also be deasserted by issuing an alert response address call. see the description in the ?smbus interface? section. the int# pin may only become active while the monitor block is operational. 6.6 low power modes the hardware monitor block can be placed in a low-power mode by writing a ?0? to bit[0] of the ready/lock/start register (0x40). the low power mode that is entered is either sleep mode or shutdown mode as selected using bit[0] of the special function re gister (7ch). these modes do not reset any of the registers of the hardware monitor block. in both of these modes, the pwm pins are at 100% duty cycle. 6.6.1 sleep mode this is a low power mode in which bias currents are ?on? but the hardware monitor block is not operating. in this mode, the a/d converter and monitoring cycle will be turned off. serial bus communication is still possible with any register in the hardware monitor block while in this low-power mode.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 26 rev. 09-09-04 datasheet 6.6.2 shutdown mode this is a low power mode in which bias currents are ?o ff? and the hardware monitor block is not operating. in this mode, the a/d converter and monitoring cycle will be turned off. serial bus communication is still possible with any register in the hardware monitor block while in this low-power mode. 6.7 analog voltage measurement ? emc6d101 monitors power supplies +2.5v, +5v, +12v, vccp, and vcc ? EMC6D100 monitors additional power supplies +3.3v, +1.5v, +1.8v the hardware monitor block contains inputs for dire ctly monitoring the power supplies (+12 v, +5 v, +3.3v, +2.5v, +1.8v, +1.5v, +vccp and vcc). these in puts are scaled internally to a internal reference source, converted via an 8 bit successive approximat ion register adc or a delta-sigma adc (analog-to- digital converter), and scaled such t hat the correct value refers to 3/ 4 scale or 192 decimal (except the vccp input). this removes the need for external resistor dividers and allows for a more accurate means of measurement since the volta ges are referenced to a known value. si nce any of these inputs can be above vcc or below ground, they are not di ode protected to the power rails. the measured values are stored in the reading registers and compared with the limit regi sters. the status bits in the interrupt status register 1, 2 and 3 are set if the measured values are outside (or equal to) the programmed limits. the vccp voltage input measures t he processor voltage, which will lie in the range of 0v to 3.0v. the following table shows the values of the analo g inputs that correspond to the min and max output codes of the a/d converter. for a complete list of the adc conver sions see appendix b. input voltage +12v in +5v in v cc /3.3v in +2.5v in +1.8v in +1.5v in +v ccp min value (corresponds to a/d output 00000000) <0.062 <0.026 <0.017 <0.013 <0.009 <0.008 <0.012 max value (corresponds to a/d output 11111111) >15.938 >6.640 >4.383 >3. 320 >2.391 >1.992 >2.988 6.8 voltage id vid0-vid4 digital inputs are used to store processor volt age id codes (for processor operating voltage) in the vid0-4 register (43h). thes e vids can be read out by the m anagement system using the smbus interface. 6.9 temperature measurement temperatures are measured internally by bandgap te mperature sensor and externally using two sets of diode sensor pins (for measuring two extern al temperatures). see subsections below. note: the temperature sensing circuitry for the two re mote diode sensors is calibrated for a pentium diode. 6.9.1 internal temperature measurement internal temperature can be measured by bandgap te mperature sensor. the m easurement is converted into digital format by internal adc. this data is converted in two?s complement format since both negative and positive temperature can be measured. this value is stored in internal (zone 2) temperature reading register (26h) and compared to the temperature limit registers (50h ? 51h). if this value violates the
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 27 rev. 09-09-04 datasheet programmed limits in the internal (zone 2) high temper ature limit register (51h) and the internal (zone 2) low temperature limit register (50h) the corresponding status bit in interrupt status register 1 is set. if auto fan option is selected, the hardware will adjust the operation of the fans accordingly. see section 7.4.2 auto fan control operating mode . 6.9.2 external temperature measurement the hardware monitor block also provides a way to measure two external temperatures using diode sensor pins (remote x+ and remote x-). the val ue is stored in the processor (zone 1) temperature reading register (25h) for remote1+ and remote1- pins. the value is stored in the remote (zone 3) temperature reading register (27h) for remote2+ and remote2- pins. if these values violate the programmed limits in the associated limit registers, then zone (1 or 3) limit exceeded status bit is set in the interrupt status register 1. if auto fan option is selected, the hardware will adjust the operation of the fans accordingly. see section 7.4.2 auto fan control operating mode on page 31. there are remote diode (1 or 2) fault status bits in interrupt status register 2 (42h), which, when one, indicate a short or open-circuit on remote thermal di ode inputs (remote x+ and remote x-). before a remote diode conversion is updated, t he status of the remote diode is che cked. in the case of a short or open-circuit on the remote thermal diode inputs, the value in the corresponding reading register will be 80h. note that this will cause the associ ated zone limit exceeded status bit to be set. the temperature change is computed by measuring the c hange in vbe at two different operating points of the diode to which the remote x+ and remote x- pins are connected. but accu racy of the measurement also depends on non-ideality factor of t he process the diode is manufactured on. 6.9.3 temperature data format temperature data can be read from the three temper ature registers. one is the internal (zone 2) temperature reading register (26h), the second is the processor (zone 1) temperature reading register (25h), and the third is the remote (zone 3) temperature reading register (27h). the following table shows several examples of the fo rmat of the temperature digital data, represented by an 8-bit, two?s complement word with an lsb equal to 1.0 0 c. temperature reading (dec) re ading (hex) digital output -127 0 c -127 81h 1000 0001 ? ? ? ? -50 0 c -50 ceh 1100 1110 ? ? ? ? -25 0 c -25 e7h 1110 0111 ? ? ? ? -1 0 c -1 ffh 1111 1111 0 0 c 0 00h 0000 0000 +1 0 c 1 01h 0000 0001 ? ? ? ? +25 0 c 25 19h 0001 1001 ? ? ? ? +50 0 c 50 32h 0011 0010 ? ? ? ?
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 28 rev. 09-09-04 datasheet temperature reading (dec) re ading (hex) digital output +127 0 c 127 7fh 0111 1111 sensor error 128 80h 1000 0000 6.9.4 offset register offset register 1 is us ed for internal (zone 2) or processor (z one 1) temperat ure reading. the offset register 1 (1fh) contain a 2's complement value whic h is added (or subtracted if the number is negative) to the temperature reading. the default value in the offset register is zero , so initially zero is always added to the temperature reading. this offset register is configured for the external temperature channel by default. it may be switched to the internal channel by setting bit 4 of the special function register to 1. 6.9.5 second offset register the offset register 2 at 1eh is for remote (zone 3) temperature reading. this register contains a 2's complement value which is added (or subtracted if the number is negative) to the second external temperature reading. note that the defau lt value in the offset register is zero, so initially zero is always added to the second temperature reading. this offs et register only applies to remote (zone 3) diode temperature reading. no conf iguration bit is required. 6.10 temperature smoothing the part implements temperature ?spike? smoothing to prev ent the fan from spinning up rapidly as a result of a spike in temperature. the sp ike smoothing registers allow the smoothing interval to be selected for each zone. see the description of registers 62h and 63h.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 29 rev. 09-09-04 datasheet chapter 7 fan control the following sections describe the various f an control and monitoring modes in the part. 7.1 general description the EMC6D100/emc6d101 device is capable of driving th ree dc fans and monitoring up to four fans with tachometer outputs in either manual fan c ontrol mode or in auto fan control mode. the fan outputs (pwmx pins) ar e controlled by a pulse width modulation (pwm) scheme. the four pins dedicated to monitoring the operation of each fan are the tach[1:4] pins. fans equipped with fan tachometer outputs may be connected to these pins to monitor the speed of the fan. 7.2 limit and configuration registers at power up, all the registers are reset to their defau lt values and pwm[1:3] are set to ?fan always on full? mode. before initiating the monitoring cycle for eith er manual or auto mode, the values in the limit and configuration registers should be set. the limit and configurat ion registers are: registers 4eh ? 53h: zone x temper ature low/high limit registers registers 54h ? 5bh: tachx minimum registers 5fh ? 61h: zone x range/fanx frequency registers 5ch ? 5eh: fanx configuration registers 62h ? 63h: min/off, zone x spike smoothing registers 64h ? 66h: fanx pwm minimum registers 67h ? 69h: zone x fan temp limit registers 6ah ? 6ch: zone x temp absolute limit ? all fans to full registers 6dh ? 6eh: zone x hysteresis the limit and configuration regist ers are defined in section chapter 8 register set on page 37. notes: 1) the start bit in register 40h ready/lock/st art register must be set to ?1? to start temperature monitoring functions. 2) setting the fan configuration register to auto mode will not take effect until after the start bit is set.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 30 rev. 09-09-04 datasheet 7.3 device set-up bios will follow the steps listed below to configur e the fan registers on the device. the registers corresponding to each function are listed. all steps ma y not be necessary if default values are acceptable. regardless of all changes made by the bios to the li mit and parameter registers during configuration, the EMC6D100/emc6d101 will continue to operate based on default values until the start bit, in the ready/lock/start register, is set. once the star t bit is set, the EMC6D100/emc6d101 will operate according to the values that were set by bios in the limit and parameter registers. 1. set limits and parameters (not necessarily in this order) a) [5f-61h] set pwm frequencies and auto fan control range. b) [62-63h] set spike smoothing and min/off c) [5c-5eh] set the fan spin-up delays. d) [5c-5eh] match each fan with a corresponding thermal zone. e) [67-69h] set the fan temperature limits. f) [6a-6ch] set the te mperature absol ute limits. g) [64-66h] set the pwm minimum duty cycle. h) [5f-61h] set the auto fan control range. i) [6d-6eh] set the temperature hysteresis values. 2. [40h] set bit 0 (start) to start monitoring. 3. [40h] set bit 1 (lock) to lock the lim it and parameter registers (optional) 7.4 pwm fan speed control note: the following description applies to pwm1, pwm2, and pwm3. when describing the operation of the pwms, the terms ?full on? and ?100% duty cycle? means that the pwm output will be high (od) for 255 clocks, and low for 1 cl ock (invert bit = 0). the exception to this is during fan spin-up when the pwm pin will be forced high (od) for the duration of the spin-up time. note: during the low time of each pwm output, the part will generate multiple positive pulses for system synchronization. see section 7.7 system synchronization on page 36 for a description of these pulses. 7.4.1 manual fan cont rol operating mode when operating in manual fan control operating mode so ftware controls the fans. the operation of the fans can be monitored based on reading the temperat ure and tachometer reading registers and/or by polling the interrupt status registers. the EMC6D100 offers the option of generating an interrupt indicated by the int# pin. to control the fans: to set the mode to operate in manual mode, write ?1 11? to bits[7:5] zone/mode, located in registers 5ch- 5eh: fan configuration. the speed of the fan is controlled by the duty cycl e set for that device. the duty cycle must be programmed in registers 30h-32h: current pwm duty to monitor the fans: if an out-of-limit condition occurs, the corresponding status bit will be set in the interrupt status registers. setting this status bit will generate an interrupt signal on the int# pin (if enabled ? EMC6D100 only). software must handle the interrupt condition and modify the operation of the EMC6D100/emc6d101 accordingly. software can evaluate the operation of the device through the temperature and fan tachometer reading registers.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 31 rev. 09-09-04 datasheet when in manual mode, the current pwm duty cycle r egisters can be written to adjust the speed of the fans, when the start bit is set. these register s are not writeable when the lock bit is set. 7.4.2 auto fan control operating mode the EMC6D100/emc6d101 chip impl ements automatic fan control. in auto fan mode, the chip automatically adjusts the pwm duty cycle of the pwm outputs, according to the flow chart below. pwm outputs are assigned to a thermal zone based on the fan configuration registers. it is possible to have more than one pwm output assigned to a thermal zone. for example, pwm outputs 2 and 3, connected to two chassis fans, may both be controlled by thermal zo ne 2. at any time, if the temperature of a zone exceeds its absolute limit, all pwm outputs go to 100% duty cycle to provide maximum cooling to the system (except those fans that are disabled). it is possible to have a single fan controlled by multiple zones, turning on when either zone requires cooling based on its individual settings. a vcc por resets all values to their initial or default st ates. if the device is not in reset and the start bit is set to ?1? the configuration and parameter registers become read only when the start bit is set and are not latched inside of the auto fan block. if the start bit is one the auto fan control block will evaluate the temperature in the zones configured for each fan in a round robin method. the auto fan co ntrol block completely evaluates the zones for all three fans in a maximum of 0.25sec.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 32 rev. 09-09-04 datasheet auto fan mode initiated temp >= abslimit (69~6b) yes override all pwm outputs to 100% duty temp >= limit (66~68) no temp >= hyst temp (6c~6d) no set fan output to 0% no set fan output to auto fan mode minimum speed. (63~65) yes fan output at 0%? no yes fan output at 0%? yes set fan speed based on auto fan range algorithm* no begin fan spin-up yes set fan output to 100% fan spinning up? spin up time elapsed? (5c-5e) yes begin polling cycle end polling cycle no no end fan spin up yes off/min set to 1? (62) no yes set fan to min pwm except if disabled figure 7.1 - automatic fan control flow diagram * see section 8.18 registers 5c-5eh: f an configuration on page 51 for details . when operating in auto fan control operating mode the hardware controls the fans directly based on monitoring of temperature and speed. to control the fans: 1. set the minimum temperat ure that will turn the f ans on/off. this value is programmed in registers 67h-69h: zone x temp limit (auto fan mode only). 2. set the hysteresis value for the minimum temperature that will turn the fans off. this value will hold the fans on until the temperature goes a certai n amount below the value programmed in the zone x temp limit registers. this value will prevent th e fan from oscillating between on and off if the
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 33 rev. 09-09-04 datasheet temperature is around the minimum temperature limi t. this value is programmed in registers 6dh- 6eh: zone hysteresis registers. 3. the speed of the fan is controlled by the duty cy cle set for that device. the duty cycle for the minimum fan speed must be programmed in register s 64h-66h: fanx pwm minimum. this value corresponds to the speed of the fan when the te mperature reading is equal to the minimum temperature limit setting. as the actual temper ature increases/decreases and is above the zone limit temperature and below the absolute temper ature limit, the pwm will be determined by a linear function based on the auto fan speed range bits in registers 5fh-61h. 4. set the absolute temperature for each zone in r egisters 6ah-6ch: absolute limit (auto fan mode only). if the actual temperature is equal to or exc eeds the absolute temperature in one or more zones, all fans will be set to full on, regardless of which zone they are operating in (except those that are disabled). note: fans can be disabled via the fan configuration registers and the absolute temperature safety feature can be disabled by writi ng 80h into the absolute temp limit registers. 5. to set the mode to operate in auto mode, set bits [7:5] zone/mode, located in registers 5ch-5eh: fan configuration: bits[7:5]=?000? for fan on zone 1; bi ts[7:5]=?001? for fan on zone 2; bits[7:5]=?010? for fan on zone 3. if the ?hottest? option is chosen (1 01 or 110), then the fan is controlled by the zone that results in the highest pwm duty cycle value. notes: software can be alerted of an out-of- limit condition by the int# pin if a status bit is set and enabled (EMC6D100 only). software can monitor the operation of the fans thro ugh the fan tachometer reading registers and by the fan x current pwm duty registers. it can also mo nitor current temperature readings through the temperature limit registers if hardware monitoring is enabled. fan control in auto mode is implemented without an y input from external processor and without any consideration of the fan tachometer register values except during spin up. see description below. in auto ?zone? mode, the speed is ad justed automatically as shown in the figure below. fans are assigned to a zone. it is possible to have more than one fan in a thermal zone or one fan monitoring two or three fans. figure 7.2 shows the control flow for the auto fan algorithm. the part allows a minimum temperature to be set, below which the fan will not run or will run at minimum speed. a hysteresis value is included to prevent the fan continuously switching on and off if the temperature is close to the minimum. a temperature range is specified over which the part will automatically adjust the fan speed. when the temperature exceeds the minimum, the fan will ?spin up? by going on full for a programmable amount of time. following this spin up time, the fan will go to a duty cycle computed by the auto fan algorithm. as the temperature rises, the duty cycle will increase until th e fan is running at full-speed when the temperature reaches the minimum plus the range value. the effect of this is a temperature feedback loop, which will cause the temperature to reach equilibrium bet ween the minimum temperature and the minimum temperature plus the range. provid ed that the fan has adequate cooling capacity for all environmental and power dissipation conditions, this system will maintain the temperature within acceptable limits, while allowing the fan to run slower (and quieter) when less cooling is required.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 34 rev. 09-09-04 datasheet pwm duty cycle temperature max min max min spin up pwm may be at min or off when below min temp hysteresis figure 7.2 - automatic fan control 7.4.3 spin up when a fan is being started from a st ationary state, the part will cause the fan to ?spin up? by going to 100% duty cycle for a programmable amount of time to over come the inertia of the fan. following this spin up time, the fan will go to a duty cycle computed by the auto fan algorithm. during spin-up, the pwm duty cycle is reported as 0%. to limit the spin-up time and ther eby reduce fan noise, the part uses feedback from the tachometers to determine when each fan has started spinning proper ly. the following tachometer feedback is included into the auto fan algorithm during spin-up. this f eature defaults to enabled; it can be disabled by clearing bit 4 of the configuration r egister (7fh). if disabled, the all fans go to 100% duty cycle for the duration of their associated spin up time. note that the ta chometer x minimum registers must be programmed to a value less than ffffh in order for the spin up reduction to work properly. 1. the pwm goes to 100% duty cycle until the tachom eter reading register is below the minimum limit, or the spin-up time expires, whichever comes first. this causes spin-up to continue until the tachometer enters the valid count r ange, unless the spin up time expires. if the spin up expires before the tachometer enters the valid rang e, an interrupt status bit will be set once spin-up expires. note that more than one tachometer may be associat ed with a pwm, in which case all tachometers associated with a pwm must be in the valid range for spin-up to end. 2. the tachometer reading register always give s the actual reading of the tachometer input. 3. no interrupt bits are set during spin-up.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 35 rev. 09-09-04 datasheet 7.4.4 hottest option if the ?hottest? option is chosen (101 or 110), then t he fan is controlled by the limits and parameters associated with the zone that requires the highest pw m duty cycle value, as calculated by the auto fan algorithm. 7.5 fan speed monitoring the chip monitors the speed of the fans by utilizing fan tac hometer input signals from fans equipped with tachometer outputs. the fan tachom eter inputs are monitored by usin g the fan tachometer registers. these signals, as well as the fan tac hometer registers, are described below. 7.5.1 fan tachometer inputs a fan tachometer input is used to measure the speed at which a fan is rotating. the fan tachometer input is a train of square pulses with a 50% duty cycle (see fig ure 7.3) that are derived fr om the magnetic fields generated by the rotating rotor of the fan. the s peed of the fan can be dete rmined by calculating the period of the fan tac hometer input pulse. note: all calculations are based on fans that emit 2 sq uare pulses per revolution. reading registers reflect a count value for one complete revolution (2 pulses). fan tachometer input clock source for counter t p t r = revolution time = 60/rpm (sec) t p = pulse time = t r /2 (two pulses per revolution) f = 90khz t r figure 7.3 - fan tachometer input and clock source the counter is used to deter mine the period of the fan tachometer i nput pulse. this counter is reset on the rising edge of every other fan tach ometer input pulse, and thus meas ures the number of clock pulses generated by the clock source for the duration of one fan tachometer revolution. since two fan tachometer input pulses are generated per revolution of the fan rotor, the speed of the fan is easily calculated. the fan tachometer input resets the counter on every other pulse and simultaneously loads the count into its respective reading register. this value is used by t he operating system to monitor the speed of the fan. the fan tachometer reading register s contain the number of 11.111us periods (90khz) between full fan revolutions. fans produce 2 pulses per revolution. the tachometer reading registers are 16 bits. the value ffffh indicates that the fan is not spinning, or the tachometer input is not connec ted to a valid signal (this could be triggered by a counter overflow). these registers are read only ? a write to these registers has no effect. the fan tachometer reading registers contain the num ber of periods of a full tachometer revolution (every two pulses). these registers are updated at l east once every second. the frequency of the clock source for the tachometer logic is 90khz. this regist er is latched on the rising edge of every other fan tachometer pulse and when the fan count reaches ffffh. this latter condition is the stalled fan event.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 36 rev. 09-09-04 datasheet 7.5.2 detection of a stalled fan the fan failure bit in the interrupt status register is set in the even t of a stalled fan. note: the fan tachometer reading register, which holds the count value, does not roll over - it stays at ffffh in the event of a stalled fan. the internal c ount register does rollover, however, and continuously counts to ffffh as long as the fan is stalled. in the event the counter reaches ffffh, the status bit is set and the count value is latched into the register. the second subsequent fan tach pulse re sets the counter but does not latch the count value. every second fan tach pulse latches the fan count value into the fan tachometer register except for this special case. the status bit for a fan failure is set when the tach reading is above the value set in the tach minimum register. this interrupt status bit cannot be cleared by reading the status register as long as the count value is above the minimum. the tachometer can generate an int# if properly enabled (EMC6D100 only). 7.5.3 fan interrupt status bits the status bits for the fan events are in interrupt stat us register 2 (42h). these bits are set when the reading register is above the tachometer minimum. no interrupt status bits are set for fan events (even if the fan is stalled) if the asso ciated tachometer minimum is set to ffffh (registers 54h-5bh). 7.6 linking fan tachometers to pwms the fan tach/pwm interrupt select register is used to link the tachometers to the pwms. this association is used by the fan logic to determine when to prevent a bit from being set in the interrupt status registers. see the description of the pwm_ tach register. the default configuration is: pwm1 -> tach1. pwm2 -> tach2. pwm3 -> tach3 & tach4. 7.7 system synchronization system synchronization pulses under normal operation, the pwm outputs will exhibit sy nchronization pulses in addition to the normal pwm pulses. these pulses are 44us in duration, and repeat every 711us. these synchronization pulses may be controlled by regi ster 83h: synch pulse conf iguration register: on/off. see section chapter 8 register set fo r a description of this register. see section chapter 10 timing diagrams on page 71 for timing diagrams that illustrate pwm or synchronization pulses, pwm?s with synchroniz ation, and pwm?s without synchronization.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 37 rev. 09-09-04 datasheet chapter 8 register set definition for the lock and start columns: yes = register is made read-only when the related bit is set; no = register is not made read-only when the related bit is set. register address read/ write register name abbr. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock start 10h r/w smsc test register smsc 7 6 5 4 3 2 1 0 00h no no 1eh r/w offset register 2 of2r 7 6 5 4 3 2 1 0 00h yes yes 1fh r/w offset register 1 of1r 7 6 5 4 3 2 1 0 00h yes yes 20h r 2.5v v25r 7 6 5 4 3 2 1 0 n/a no no 21h r vccp vcpr 7 6 5 4 3 2 1 0 n/a no no 22h r vcc vccr 7 6 5 4 3 2 1 0 n/a no no 23h r 5v v50r 7 6 5 4 3 2 1 0 n/a no no 24h r 12v v12r 7 6 5 4 3 2 1 0 n/a no no 25h r processor (zone1) temp trd1 7 6 5 4 3 2 1 0 n/a no no 26h r internal (zone2) temp tamr 7 6 5 4 3 2 1 0 n/a no no 27h r remote (zone3) temp trd2 7 6 5 4 3 2 1 0 n/a no no 28h r tach1 lsb ftl1 7 6 5 4 3 2 1 0 n/a no no 29h r tach1 msb ftm1 15 14 13 12 11 10 9 8 n/a no no 2ah r tach2 lsb ftl2 7 6 5 4 3 2 1 0 n/a no no 2bh r tach2 msb ftm2 15 14 13 12 11 10 9 8 n/a no no 2ch r tach3 lsb ftl3 7 6 5 4 3 2 1 0 n/a no no 2dh r tach3 msb ftm3 15 14 13 12 11 10 9 8 n/a no no 2eh r tach4 lsb ftl4 7 6 5 4 3 2 1 0 n/a no no 2fh r tach4 msb ftm4 15 14 13 12 11 10 9 8 n/a no no 30h r/w 1 fan1 current pwm duty fcd1 7 6 5 4 3 2 1 0 n/a yes 1 no 1 31h r/w 1 fan2 current pwm duty fcd2 7 6 5 4 3 2 1 0 n/a yes 1 no 1 32h r/w 1 fan3 current pwm duty fcd3 7 6 5 4 3 2 1 0 n/a yes 1 no 1 3eh r company id coid 7 6 5 4 3 2 1 0 5ch no no 3fh r version / stepping stnv ver3 ver2 ver1 ver0 stp3 stp2 stp1 stp0 60h no no 40h r/w 2 ready/lock/start rlst res res res res ovrid ready lock start 00h yes 2 no 41h r-c 3 interrupt status register 1 int1 int23 zn3 zn2 zn1 5v vcc vccp 2.5v 00h no no 42h r-c 3 interrupt status register 2 int2 e rr2 err1 fan4 fan3 fan2 fan1 res 12v 00h no no 43h r vid0-4 vidr res res res vid4 vid3 vid2 vid1 vid0 n/a no no 44h r/w 2.5v low limit v25l 7 6 5 4 3 2 1 0 00h no yes 45h r/w 2.5v high limit v25h 7 6 5 4 3 2 1 0 ffh no yes 46h r/w vccp low limit vcpl 7 6 5 4 3 2 1 0 00h no yes 47h r/w vccp high limit vcph 7 6 5 4 3 2 1 0 ffh no yes 48h r/w vcc low limit vccl 7 6 5 4 3 2 1 0 00h no yes 49h r/w vcc high limit vcch 7 6 5 4 3 2 1 0 ffh no yes
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 38 rev. 09-09-04 datasheet register address read/ write register name abbr. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock start 4ah r/w 5v low limit v50l 7 6 5 4 3 2 1 0 00h no yes 4bh r/w 5v high limit v50h 7 6 5 4 3 2 1 0 ffh no yes 4ch r/w 12v low limit v12l 7 6 5 4 3 2 1 0 00h no yes 4dh r/w 12v high limit v12h 7 6 5 4 3 2 1 0 ffh no yes 4eh r/w processor (zone1) low temp trl1 7 6 5 4 3 2 1 0 81h no yes 4fh r/w processor (zone1) high temp trh1 7 6 5 4 3 2 1 0 7fh no yes 50h r/w internal (zone2) low temp tall 7 6 5 4 3 2 1 0 81h no yes 51h r/w internal (zone2) high temp tahl 7 6 5 4 3 2 1 0 7fh no yes 52h r/w remote (zone3) low temp trl2 7 6 5 4 3 2 1 0 81h no yes 53h r/w remote (zone3) high temp trh2 7 6 5 4 3 2 1 0 7fh no yes 54h r/w tach1 minimum lsb fml1 7 6 5 4 3 2 1 0 ffh no yes 55h r/w tach1 minimum msb fmm1 15 14 13 12 11 10 9 8 ffh no yes 56h r/w tach2 minimum lsb fml2 7 6 5 4 3 2 1 0 ffh no yes 57h r/w tach2 minimum msb fmm2 15 14 13 12 11 10 9 8 ffh no yes 58h r/w tach3 minimum lsb fml3 7 6 5 4 3 2 1 0 ffh no yes 59h r/w tach3 minimum msb fmm3 15 14 13 12 11 10 9 8 ffh no yes 5ah r/w tach4 minimum lsb fml4 7 6 5 4 3 2 1 0 ffh no yes 5bh r/w tach4 minimum msb fmm4 15 14 13 12 11 10 9 8 ffh no yes 5ch r/w fan 1 configuration fcf1 zon2 zon1 zon0 inv res spin2 spin1 spin0 62h yes yes 5dh r/w fan 2 configuration fcf2 zon2 zon1 zon0 inv res spin2 spin1 spin0 62h yes yes 5eh r/w fan 3 configuration fcf3 zon2 zon1 zon0 inv res spin2 spin1 spin0 62h yes yes 5fh r/w zone 1 range/fan 1 frequency frf1 ran3 ran2 ran1 ran0 res frq2 frq1 frq0 c3h yes yes 60h r/w zone 2 range/fan 2 frequency frf2 ran3 ran2 ran1 ran0 res frq2 frq1 frq0 c3h yes yes 61h r/w zone 3 range/fan 3 frequency frf3 ran3 ran2 ran1 ran0 res frq2 frq1 frq0 c3h yes yes 62h r/w min/off, zone 1 spike smoothing ssz1 off3 off2 off1 res zn1e zn1-2 zn1-1 zn1-0 00h yes yes 63h r/w zone 2, zone 3 spike smoothing ss23 zn2e zn2-2 zn2-1 zn2-0 zn3e zn3-2 zn3-1 zn3-0 00h yes yes 64h r/w fan1 pwm minimum dcm1 7 6 5 4 3 2 1 0 80h yes yes 65h r/w fan2 pwm minimum dcm2 7 6 5 4 3 2 1 0 80h yes yes 66h r/w fan3 pwm minimum dcm3 7 6 5 4 3 2 1 0 80h yes yes 67h r/w zone 1 fan temp limit tlf1 7 6 5 4 3 2 1 0 5ah yes yes 68h r/w zone 2 fan temp limit tlf2 7 6 5 4 3 2 1 0 5ah yes yes 69h r/w zone 3 fan temp limit tlf3 7 6 5 4 3 2 1 0 5ah yes yes 6ah r/w zone 1 temp absolute limit taf1 7 6 5 4 3 2 1 0 64h yes yes 6bh r/w zone 2 temp absolute limit taf2 7 6 5 4 3 2 1 0 64h yes yes 6ch r/w zone 3 temp absolute limit taf3 7 6 5 4 3 2 1 0 64h yes yes
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 39 rev. 09-09-04 datasheet register address read/ write register name abbr. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock start 6dh r/w zone 1, zone 2 hysteresis hy12 h1-3 h1-2 h1-1 h1-0 h2-3 h2-2 h2-1 h2-0 44h yes yes 6eh r/w zone 3, hysteresis hys3 h3-3 h3-2 h3-1 h3-0 res res res res 40h yes yes 6fh r/w xor test tree enable xort res res res res res res res xen 00h yes yes 70h r +3.3v reading v33r 7 6 5 4 3 2 1 0 na no no 71h r +1.5 reading v15r 7 6 5 4 3 2 1 0 na no no 72h r +1.8 reading v18r 7 6 5 4 3 2 1 0 na no no 73h r/w +3.3v low limit v33l 7 6 5 4 3 2 1 0 00h no yes 74h r/w +3.3v high limit v33h 7 6 5 4 3 2 1 0 ffh no yes 75h r/w +1.5 low limit v15l 7 6 5 4 3 2 1 0 00h no yes 76h r/w +1.5 high limit v15h 7 6 5 4 3 2 1 0 ffh no yes 77h r/w +1.8 low limit v18l 7 6 5 4 3 2 1 0 00h no yes 78h r/w +1.8 high limit v18h 7 6 5 4 3 2 1 0 ffh no yes 79h r/w test mode register motr antst2 antst1 antst0 oscsel adcavg extclk digtst adctst 00h yes yes 7ah r error debug register erdr res ara stop invadd rcv rowr invrw nonac 00h no no 7bh r/w test digital value register dvtr 7 6 5 4 3 2 1 0 00h yes yes 7ch r/w 4 special function register sftr d2en d1en avg offcfg volten inten monmd lpmd e0h yes 4 yes 4 7dh r-c 3 interrupt status register 3 int3 res res res res res 33v 18v 15v 00h no no 7eh r/w interrupt enable inte vcc 12v 5v 33v vccp 25v 18v 15v ech yes yes 7fh r/w configuration conf init fttst res suren trdy res p4int res 10h yes yes 80h r/w fan temp interrupt enable ftie res amb temp fan4 fan3 fan2 fan1 fan 5eh yes yes 81h r/w fan tach/pwm interrupt select ftis t4h t4l t3h t3l t2h t2l t1h t1l a4h yes yes 82h r/w reserved n/a res res res res res res res res ffh yes no 83h r/w sync pulse configuration register: on/off fcf4 res res res on res res res res 62h yes yes 84h r/w reserved n/a res res res res res res res res 03h yes yes 85h r/w reserved n/a res res res res res res res res 80h yes yes 86h r smooth remote diode reading 1 srd1 7 6 5 4 3 2 1 0 n/a no no 87h r smooth ambient reading samr 7 6 5 4 3 2 1 0 n/a no no 88h r smooth remote diode reading 2 srd2 7 6 5 4 3 2 1 0 n/a no no 89h r adc 2 lsb test adtr 7 6 5 4 3 2 1 0 n/a no no 8ah r input test reg 1 cbi1 res 6 5 4 3 2 1 0 4dh no no 8bh r/w output test reg 1 cbo1 7 6 5 4 3 2 1 0 4dh yes yes 8ch r input test reg 2 cbi2 res res res 4 3 2 1 0 0eh no no 8dh r/w output test reg 2 cbo2 res res res 4 3 2 1 0 0eh yes yes notes: 1. the fan x current duty cycle registers are only writeable when the associated fan is in manual mode. in this case, the register is writeable when the start bit is set, but not when the lock bit is set. 2. the lock and start bits in the ready/lock/start r egister are locked by the lock bit. the ovrid bit is always writeable, both wh en the start bit is set and when the lock bit is set.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 40 rev. 09-09-04 datasheet 3. the interrupt status registers are cleared on a read if no events are active. 4. the inten bit in register 7ch is always writeab le, both when the start bit is set and when the lock bit is set. 8.1 undefined registers the registers shown in the table above are the defined registers in t he part. any reads to undefined registers always return 00h. writes to undefined regi sters have no effect and do not return an error. 8.2 register 10h: smsc test register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 10h r/w smsc test 7 6 5 4 3 2 1 0 00h setting the lock bit has no effect on this register. this register must not be written. writing this register may produce unexpected results. 8.3 register 1e, 1fh: offset registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 1eh r/w offset register 2 7 6 5 4 3 2 1 0 00h 1fh r/w offset register 1 7 6 5 4 3 2 1 0 00h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. offset register 2 only applies to the remote diode temperature reading 2. this register contains a 2's complement value which is added (or subtracted if t he number is negative) to external temperature reading 2. the default value in the offset register is zero, so initiall y zero is always added to the temperature reading. offset register 1 applies to the remote diode temperature reading 1 or th e ambient reading. this register contains a 2's complement value which is added (or su btracted if the number is negative) to either the internal or external temperature 1 reading. the default val ue in the offset register is zero, so initially zero is always added to the temperature reading. the offset register is configured for the external temperature 1 channel by default. it may be switched to the internal channel by setting bit 4 of the special function register to 1. 8.4 registers 20-24h, 70-72h : voltage reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 20h r 2.5v 7 6 5 4 3 2 1 0 n/a 21h r vccp 7 6 5 4 3 2 1 0 n/a
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 41 rev. 09-09-04 datasheet register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 22h r 3.3v 7 6 5 4 3 2 1 0 n/a 23h r 5v 7 6 5 4 3 2 1 0 n/a 24h r 12v 7 6 5 4 3 2 1 0 n/a 70h r +3.3v 7 6 5 4 3 2 1 0 n/a 71h r +1.5v 7 6 5 4 3 2 1 0 n/a 72h r +1.8v 7 6 5 4 3 2 1 0 n/a note: registers 70h-72h are only applicable to the EMC6D100. the voltage reading registers reflect the current vo ltage of the EMC6D100/emc6d101 voltage monitoring inputs. voltages are presented in the registers at ? full scale for the nominal voltage, meaning that at nominal voltage, each register will read c0h. table 8.1 - voltage vs. register reading input nominal voltage register reading at nominal voltage maximum voltage register reading at maximum voltage minimum voltage register reading at minimum voltage 1.5v 1.5v c0h 1.99v ffh 0v 00h 1.8v 1.8v c0h 2.39v ffh 0v 00h 2.5v 2.5v c0h 3.32v ffh 0v 00h vccp 2.25v c0h 3.00v ffh 0v 00h vcc 3.3v c0h 4.38v ffh 0v 00h 3.3v 3.3v c0h 4.38v ffh 0v 00h 5v 5.0v c0h 6.64v ffh 0v 00h 12v 12.0v c0h 16.00v ffh 0v 00h the voltage reading registers will be updated automatically by the EMC6D100/emc6d101 chip with a minimum frequency of 4hz. these registers are read only ? a write to these registers has no effect. 8.5 registers 25-27h: temperature reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 25h r processor (zone1) temp 7 6 5 4 3 2 1 0 n/a 26h r internal (zone2) temp 7 6 5 4 3 2 1 0 n/a 27h r remote (zone3) temp 7 6 5 4 3 2 1 0 n/a the temperature reading registers reflect the current temperatures of the internal and remote diodes. processor (zone1) temp register reports the temper ature measured by the remo te1- and remote1+ pins, remote (zone3) temp register reports the temper ature measured by the remote2- and remote2+ pins and the internal (zone2) temp register reports t he temperature measured by the internal (ambient) temperature sensor. current temper atures are represented as 8 bit, 2?s complement, signed numbers in celsius, as shown below in table 8.2. the temperatur e reading register will return a value of 80h if the remote diode pins are not implemented by the board designer or are not functioning properly (this corresponds to the diode fault interrupt status bits ). the temperature reading registers will be updated automatically by the EMC6D100/emc6d101 chip with a minimum frequency of 4hz. these registers are read only ? a write to these registers has no effect.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 42 rev. 09-09-04 datasheet table 8.2 - temperature vs. register reading temperature reading (dec) reading (hex) -127 c -127 81h ? ? ? -50 c -50 ceh ? ? ? 0 c 0 00h ? ? ? 50 c 50 32h ? ? ? 127 c 127 7fh (sensor error) 80h 8.6 registers 28-2fh: fan tachometer reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 28h r tach1 lsb 7 6 5 4 3 2 1 0 n/a 29h r tach1 msb 15 14 13 12 11 10 9 8 n/a 2ah r tach2 lsb 7 6 5 4 3 2 1 0 n/a 2bh r tach2 msb 15 14 13 12 11 10 9 8 n/a 2ch r tach3 lsb 7 6 5 4 3 2 1 0 n/a 2dh r tach3 msb 15 14 13 12 11 10 9 8 n/a 2eh r tach4 lsb 7 6 5 4 3 2 1 0 n/a 2fh r tach4 msb 15 14 13 12 11 10 9 8 n/a the fan tachometer reading regist ers contain the number of 11.111 s periods (90khz) between full fan revolutions. fans produce two tachometer pulses per full revolution. these registers are updated at least once every second. this value is represented for each fan in a 16 bit, unsigned number. the fan tachometer reading registers always retu rn an accurate fan tachometer measurement, even when a fan is disabled or non-functional, including when the start bit=0. when one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. the order is lsb first, msb second. ffffh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow). these registers are read only ? a write to these registers has no effect. 8.7 registers 30-32h: current pwm duty register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 30h r/w 1 fan1 current 7 6 5 4 3 2 1 0 n/a
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 43 rev. 09-09-04 datasheet register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value pwm duty 31h r/w 1 fan2 current pwm duty 7 6 5 4 3 2 1 0 n/a 32h r/w 1 fan3 current pwm duty 7 6 5 4 3 2 1 0 n/a note 1: these registers are only writeable when the asso ciated fan is in manual mode. these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. the current pwm duty registers store the duty cycl e that the EMC6D100/emc6d101 chip is currently driving the pwm signals at. at init ial power-on, the duty cycle is 100% and thus, when read, this register will return ffh. after the ready/lock/start register start bit is set, this register and the pwm signals are updated based on the algorithm described in the auto fan control operating mode section, unless the associated fan is in manual mode ? see below. when read, the current pwm duty registers return the current pwm duty cycle for the respective pwm signal. these registers are read only ? a write to these registers has no effect. note: if the current pwm duty cycle registers are written while the part is not in manual mode and the start bit is zero, data will be stored in a hidden registers t hat will only be active and observable when the start bit is set. while the part is not in manual mode and the start bit is zero, the current pwm duty cycle registers will read back ffh. 8.7.1 manual mode in manual mode, the current duty cycle registers ar e writeable to control the pwms. in manual mode, when the start bit is set to 1, the current duty cycle registers are writeable to control the pwms. also in manual mode, when the lock bit is set to 1, the current duty cycle registers are read-only. the pwm duty cycle is represented as follows: table 8.3 - pwm duty vs. register reading current duty value (decimal) value (hex) 0% 0 00h ? ? ? 25% 64 40h ? ? ? 50% 128 80h ? ? ? 100% 255 ffh during spin-up, the pwm duty cycle is reported as 0%.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 44 rev. 09-09-04 datasheet 8.8 register 3eh: company id register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3eh r company id 7 6 5 4 3 2 1 0 5ch the company id register contains the company identification number. this number is a method for uniquely identifying the pa rt manufacturer. this register is read only ? a write to this register has no effect. 8.9 register 3fh: version / stepping register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3fh r version / stepping ver3 ver2 ver1 ver0 stp3 stp2 stp1 stp0 60h the four least significant bits of the version / stepping register [3:0 ] contain the current stepping of the EMC6D100/emc6d101 silicon. the four most signifi cant bits [7:4] reflect the EMC6D100/emc6d101 version number. the EMC6D100/emc6d101 has a fixed version number of 0110b. for the a0 stepping of EMC6D100/emc6d101, this register will read 01100000b. for the a1 stepping of the EMC6D100/emc6d101, this register will read 01100001b. the register is used by application software to identi fy which device in the emc family of monitoring asics has been implemented in the given system. based on this information, software can determine which registers to read from and write to. further, app lication software may use the current stepping to implement work-arounds for bugs f ound in a specific silicon stepping. this register is read only ? a write to this register has no effect. 8.10 register 40h: ready/lock/start monitoring register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 40h r/w ready/lock/st art res res res res ovr id rea dy loc k sta rt 00h setting the lock bit makes the lock and start bits read-only.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 45 rev. 09-09-04 datasheet bit name r/w default description 0 start r/w 0 when software writes a 1 to this bit, the EMC6D100/emc6d101 enables monitoring and pwm output control f unctions based on the limit and parameter registers. before this bit is set, the part does not update register values. whenever this bit is set to 0, the monitoring and pwm output control functions are based on the default limits and parameters, regardless of the current values in th e limit and parameter registers. the EMC6D100/emc6d101 preserves the values currently stored in the limit and parameter registers when this bit is set or cleared. this bit becomes read only when the lock bit is set. note: when this bit is 0, all fans ar e on full 100% duty cycle, i.e., pwm pins are high (od) for 255 clocks, low for 1 clock. when this bit is 0, the part is not monitoring. it is expected that all limit and paramet er registers will be set by bios or application software prior to setting this bit because these registers cannot be written once the start bit is set. 1 lock r/w 0 setting this bit to 1 locks specified limit and parameter registers. once this bit is set, limit and parameter registers become read only and will remain locked until the device is powered off. this register bit becomes read only once it is set. 2 ready r 0 the EMC6D100/emc6d101 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all a/d converters are functioning (all bias conditions for the a/ds have stabilized and the a/ds are in operational mode). (always reads back ?1?.) 3 ovrid r/w 0 if this bit is set to 1, all pwm outputs go to 100% duty cycle regardless of whether or not the lock bit is set. 4-7 reserved r 0 reserved note: there is a start-up time of up to 82ms for monitoring after the start bit is set to ?1?, during which time the reading registers are not valid. the following summarizes the operation of the part based on the start bit: 1. if start bit = '0' then: a) fans are set to full on. b) no voltage, temperature, or f an tach monitoring is performed. the values in the reading registers will be n/a (not applicable), which means these values will not be considered valid readings until the start bit = '1'. the exception to this is the tachometer reading regist ers, which always give the actual reading on the tach pins. c) no status bits are set. 2. if start bit = '1' then: a) all fan control and monitoring will be based on the current values in the r egisters. there is no need to preserve the default values after soft ware has programmed these registers because no monitoring or auto fan control will be done when start bit = '0'. b) status bits may be set. c) the limit and parameter regist ers are read-only when the start bit is 1. only the current pwm duty cycle and ready/lock /start registers are writeable when the associated fan is in manual mode. the inten bit in register 7ch is also writeable when the start bit is set. note: once programmed, the register values will be saved when start bit is reset to ?0?.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 46 rev. 09-09-04 datasheet 8.11 register 41h: interrupt status register 1 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 41h r-c 1 interrupt status 1 int23 zn3 zn2 zn1 5v 3.3v vccp 2.5v 00h note 1: this register is cleared on a read if no events are active the interrupt status register 1 bits are automatically set by t he EMC6D100/emc6d101 whenever the 2.5v, vccp, 3.3v, or 5v input voltages violate the limi ts set in the limit and param eter registers or when the measured temperature violates the limits set in t he limit and parameter regist ers for any of the three thermal zones. this register holds a set bit until the event is read by software. the contents of this register are cleared (set to 0) automatically by the EMC6D100/emc6d101 after it is read by software, if the voltage or temperature no longer violates the limits set in the lim it and parameter registers. once set, the interrupt status register 1 bits remain set until a read even t occurs, even if the voltag e or temperature no longer violate the limits set in the limit and parameter registers. this register contains a bit that indicates that a bit is set in one of the other interrupt status registers. if bit 7 is set, then a status bit is set in either interrupt stat us register 2 or 3 (or both) . therefore, s/w can poll this register, and only if bit 7 is set do the other regi sters need to be read. this bit is cleared (set to 0) automatically by the EMC6D100/emc6d1 01 if there are no bits set in inte rrupt status registers 2 and 3. this register is read only ? a write to this register has no effect. bit name r/w default description 0 2.5v_error r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the 2.5v input voltage is less than or equal to the limit set in the 2.5v low limit register or greater than the limit set in the 2.5v high limit register. 1 vccp_error r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the vccp input voltage is less than or equal to the limit set in the vccp low limit register or greater than the limit set in the vccp high limit register. 2 3.3v_error r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the 3.3v input voltage is less than or equal to the limit set in the 3.3v low limit register or greater than the limit set in the 3.3v high limit register. 3 5v_error r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the 5v input voltage is less than or equal to the limit set in the 5v low limit register or greater t han the limit set in the 5v high limit register. 4 zone 1 limit exceeded r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the temperature input measured by the remote1- and remote1+ is less than or equal to the limit set in the processor (zone1) low temp register or greater than the limit set in processor (zone1) high temp register. 5 zone 2 limit exceeded r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the temperature input measured by the internal temperature sensor is less than or equal to the limit set in the internal (zone2) low temp register or greater than the limit set in the internal (zone2) high temp register. 6 zone 3 limit exceeded r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the temperature input measured by the remote2- and remote2+ is less than or equal to the limit set in the remote (zone3) low temp register or greater than the limit set in the remote (zone3) high temp register.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 47 rev. 09-09-04 datasheet bit name r/w default description 7 int2, 3 event active r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when a status bit is set in either in terrupt status register 2 or 3. 8.12 register 42h: interrupt status register 2 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 42h r-c 1 interrupt status register 2 err2 err1 fan4 fan3 fan2 fan1 res 12v 00h note 1: this register is cleared on a read if no events are active the interrupt status register 2 bits is automatica lly set by the EMC6D100/emc6d101 whenever a remote temperature sensor error occurs, a fan is above the minimum speed set in the tachometer minimum registers, or whenever the 12v input voltage violates the limits set in the limit and parameter registers. the interrupt status register 2 register holds a set bit until the event is read by software. the contents of this register are cleared (set to 0) automatically by the EMC6D100/emc6d101 after it is read by software, if the voltage or temperature no lon ger violates the limits set in the limit and parameter registers, or if the fan reading regi ster is no longer above the minimum. once set, the interrupt status register 2 bits remain set until a read event occurs, ev en if the voltage or temperat ure no longer violates the limits set in the limit and parameter registers or if the fan reading register is below the minimum. the remote diode fault bits do not clear on a read while the fault condition exists. a fault event loads 80h into the associated temperature reading register when the start bit is set, which will cause the associated diode limit error bit to be set (zone 1 limit exceeded or zone 3 limit exceeded) in addition to the diode fault bit. disabling the enable bit for the diode will clear both the fault bit and the error bit for that diode. this register is read only ? a write to this register has no effect. bit name r/w default description 0 +12v_error r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the 12v input voltage is less than or equal to the limit set in the 12v low limit register or greater than the limit set in the 12v high limit register. 1 reserved r 0 reserved 2 fan1 stalled r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the tach1 input reading is above the value set in the tach1 minimum msb and lsb registers. 3 fan2 stalled r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the tach2 input reading is above the value set in the tach2 minimum msb and lsb registers. 4 fan3 stalled r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the tach3 input reading is above the value set in the tach3 minimum msb and lsb registers. 5 fan4 stalled r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when the tach4 input reading is above the value set in the tach4 minimum msb and lsb registers. 6 remote diode 1 fault r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when there is either a short or open circuit fault on the remote1+ or remote1- thermal diode input pins. 7 remote diode 2 fault r 0 the EMC6D100/emc6d101 automatically sets this bit to 1 when there is either a short or open circuit fault on the remote2+ or remote2- thermal diode input pins.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 48 rev. 09-09-04 datasheet 8.13 register 7dh: interrupt status register 3 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7dh r-c 1 interrupt status register 3 res res res res res 33v 18v 15v 00h note 1: this register is cleared on a read if no events are active note: this register only applies to the EMC6D100. the interrupt status register 3 bi ts are automatically set by the em c6d100 whenever the 1.5v, 1.8v, or 3.3v input voltages violate the limits set in the limit and parameter registers. this register holds a set bit until the event is read by software. the contents of this register is cleared (set to 0) automatically by the EMC6D100 after it is read by software, if the voltage no longer violates the limit set in the limit and parameter register. once set, the interrupt status register 3 bits remain set until a read event occurs, even if the voltage or temperature no longer violates the limits set in the limit and parameter registers. this register is read only ? a write to this register has no effect. bit name r/w default description 0 +1.5v_error r 0 the EMC6D100 automati cally sets this bit to 1 when the 1.5v input voltage is less than or equa l to the limit set in the 1.5v low limit register or greater than the limit set in the 1.5v high limit register. 1 +1.8v_error r 0 the EMC6D100 automati cally sets this bit to 1 when the 1.8v input voltage is less than or equa l to the limit set in the 1.8v low limit register or greater than the limit set in the 1.8v high limit register. 2 +3.3v_error r 0 the EMC6D100 automati cally sets this bit to 1 when the 3.3v input voltage is less than or equa l to the limit set in the 3.3v low limit register or greater than the limit set in the 3.3v high limit register. 3-7 reserved r 0 reserved 8.14 register 43h: vid register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 43h r vid0-4 res res res vid4 vid3 vid2 vid1 vid0 n/a the vid register contains the va lues of EMC6D100/emc6d101 vid0-vid4 input pins. this register indicates the status of the vid lines that interconn ect the processor to the voltage regulator module (vrm). software uses the information in this regist er to determine the voltage that the processor is designed to operate at. with this information, software can then dynamically determine the correct values to place in the vccp low limit and vccp high limit registers. this register is read only ? a write to this register has no effect.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 49 rev. 09-09-04 datasheet 8.15 registers 44-4dh, 73-78h: voltage limit registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 44h r/w 2.5v low limit 7 6 5 4 3 2 1 0 00h 45h r/w 2.5v high limit 7 6 5 4 3 2 1 0 ffh 46h r/w vccp low limit 7 6 5 4 3 2 1 0 00h 47h r/w vccp high limit 7 6 5 4 3 2 1 0 ffh 48h r/w vcc low limit 7 6 5 4 3 2 1 0 00h 49h r/w vcc high limit 7 6 5 4 3 2 1 0 ffh 4ah r/w 5v low limit 7 6 5 4 3 2 1 0 00h 4bh r/w 5v high limit 7 6 5 4 3 2 1 0 ffh 4ch r/w 12v low limit 7 6 5 4 3 2 1 0 00h 4dh r/w 12v high limit 7 6 5 4 3 2 1 0 ffh 73h r/w 3.3v low limit 7 6 5 4 3 2 1 0 00h 74h r/w 3.3v high limit 7 6 5 4 3 2 1 0 ffh 75h r/w 1.5 low limit 7 6 5 4 3 2 1 0 00h 76h r/w 1.5 high limit 7 6 5 4 3 2 1 0 ffh 77h r/w 1.8 low limit 7 6 5 4 3 2 1 0 00h 78h r/w 1.8 high limit 7 6 5 4 3 2 1 0 ffh note: registers 73h-78h are applicable to the EMC6D100 only. setting the lock bit has no ef fect on these registers. if a voltage input either exceeds the value set in the voltage high limit register or falls below or equals the value set in the voltage low limit register, the co rresponding bit will be set automatically by the EMC6D100/emc6d101 in the interrupt status registers (41-42h, 7dh). voltages are presented in the registers at ? full scale for the nominal voltage, meani ng that at nominal voltage, each input will be c0h, as shown in table 8.4. table 8.4 ? voltage limits vs. register setting input nominal voltage register setting at nominal voltage maximum voltage register setting at maximum voltage minimum voltage register setting at minimum voltage 1.5v 1.5v c0h 1.99v ffh 0v 00h 1.8v 1.8v c0h 2.39v ffh 0v 00h 2.5v 2.5v c0h 3.32v ffh 0v 00h vccp 2.25v c0h 3.00v ffh 0v 00h vcc 3.3v c0h 4.38v ffh 0v 00h 3.3v 3.3v c0h 4.38v ffh 0v 00h 5v 5.0v c0h 6.64v ffh 0v 00h 12v 12.0v c0h 16.00v ffh 0v 00h note: the voltages 1.5v, 1.8v and 3.3v in the tabl e above are applicable to the EMC6D100 only.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 50 rev. 09-09-04 datasheet 8.16 registers 4e-53h: temperature limit registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 4eh r/w processor (zone1) low temp 7 6 5 4 3 2 1 0 81h 4fh r/w processor (zone1) high temp 7 6 5 4 3 2 1 0 7fh 50h r/w internal (zone2) low temp 7 6 5 4 3 2 1 0 81h 51h r/w internal (zone2) high temp 7 6 5 4 3 2 1 0 7fh 52h r/w remote (zone3) low temp 7 6 5 4 3 2 1 0 81h 53h r/w remote (zone3) high temp 7 6 5 4 3 2 1 0 7fh setting the lock bit has no ef fect on these registers. if an external temperature input or the internal temperat ure sensor either exceeds the value set in the high limit register or falls below the value set in the low limit register, the corresponding bit will be set automatically by the EMC6D100/emc6d101 in the interrup t status register 1 (41h). for example, if the temperature read from the remote1- and remote2+ inputs exceeds the processor (zone1) high temp register limit setting, interrupt st atus register 1 zn1 bit will be set. the temperature limits in these registers are represented as 8 bit, 2?s complement, signed numbers in celsius, as shown below in table 8.5. table 8.5 - temperature limits vs register settings temperature limit (dec) limit (hex) -127 c -127 81h ? ? ? -50 c -50 ceh ? ? ? 0 c 0 00h ? ? ? 50 c 50 32h ? ? ? 127 c 127 7fh
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 51 rev. 09-09-04 datasheet 8.17 registers 54-5bh: fan tachometer low limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 54h r/w tach1 minimum lsb 7 6 5 4 3 2 1 0 ffh 55h r/w tach1 minimum msb 15 14 13 12 11 10 9 8 ffh 56h r/w tach2 minimum lsb 7 6 5 4 3 2 1 0 ffh 57h r/w tach2 minimum msb 15 14 13 12 11 10 9 8 ffh 58h r/w tach3 minimum lsb 7 6 5 4 3 2 1 0 ffh 59h r/w tach3 minimum msb 15 14 13 12 11 10 9 8 ffh 5ah r/w tach4 minimum lsb 7 6 5 4 3 2 1 0 ffh 5bh r/w tach4 minimum msb 15 14 13 12 11 10 9 8 ffh setting the lock bit has no ef fect on these registers. the fan tachometer low limit registers indicate t he tachometer reading under which the corresponding bit will be set in the interrupt status register 2 regist er. in auto fan control mode, the fan can run at low speeds, so care should be taken in software to ens ure that the limit is low enough not to cause sporadic alerts. the fan tachometer will not cause a bit to be set in t he interrupt status register if the current value in current pwm duty registers is 00h or if the fan is disabled via the fan configuration register. interrupts will never be generated for a fan if its tachometer minimum is set to ffffh. 8.18 registers 5c-5eh: fan configuration register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 5ch r/w fan 1 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h 5dh r/w fan 2 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h 5eh r/w fan 3 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. 8.18.1 bits [7:5] zone/mode bits [7:5] of the fan configuration registers associ ate each fan with a temperature sensor. when in auto fan mode, the fan will be assigned to a zone, and its pwm duty cycle will be adjusted according to the temperature of that zone. if ?hottest? option is selected (101 or 110), the fa n will be controlled by the hottest of zones 2 and 3, or of zones 1, 2, and 3. if one of these options is se lected, the fan is controlled by the
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 52 rev. 09-09-04 datasheet limits and parameters for the zone that requires the highest pwm duty cycle, as computed by the auto fan algorithm. when in manual control mode, the current pwm duty registers (30h-32h) become read/write. it is then possible to control the pwm outputs with software by writing to these registers. see current pwm duty registers description. when the fan is disabled (100) the corresponding pw m output is driven low (or high, if inverted). zone 1: external diode 1 (processor) zone 2: internal sensor zone 3: external diode 2 table 8.6 - fan zone setting zon[7:5] fan configuration 000 fan on zone 1 auto 001 fan on zone 2 auto 010 fan on zone 3 auto 011 fan always on full 100 fan disabled 101 fan controlled by hottest of zones 2,3 110 fan controlled by ho ttest of zones 1,2,3 111 fan manually controlled 8.18.2 bit [4] pwm invert bit [4] inverts the pwm outp ut. if set to 1, 100% duty cycle will yield an output that is low for 255 clocks and high for 1 clock. if set to 0, 100% duty cycle will yield an output that is high for 255 clocks and low for 1 clock. 8.18.3 bit [3] reserved 8.18.4 bits [2:0] spin up bits [2:0] specify the ?spin up? time for the fan. when a fan is being started from a stationary state, the pwm output is held at 100% duty cycle for the time s pecified in the table below before scaling to a lower speed. note: during spin-up, the pwm pin is forc ed high (od) for the duration of the spin-up time. note: to reduce the spin-up time, the part uses feedb ack from the tachometers to determine when each fan has started spinning properly. spin up for a pw m will end when the tachometer reading register is below the minimum limit, or the spin-up time expires, whichever comes first. all tachs associated with a pwm must be below min for spin-up to end. this feature can be disabled by clearing bit 4 of the configuration register (7fh). if dis abled, the all fans go on full for the dur ation of their associated spin up time. note that the tachx minimum registers must be programmed to a value less than ffffh in order for the spin up reduction to work properly.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 53 rev. 09-09-04 datasheet table 8.7 - fan spin-up register spin[2:0] spin up time 000 0 sec 001 100ms 010 250ms (default) 011 400ms 100 700ms 101 1000ms 110 2000ms 111 4000ms 8.19 registers 5f-61h: auto fa n speed range, pwm frequency register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 5fh r/w fan 1 range/frequency ran3 ran2 ran1 ran0 res frq2 frq1 frq0 c3h 60h r/w fan 2 range/frequency ran3 ran2 ran1 ran0 res frq2 frq1 frq0 c3h 61h r/w fan 3 range/frequency ran3 ran2 ran1 ran0 res frq2 frq1 frq0 c3h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. in auto fan mode, when the temperature for a zone is above the temperature limit (registers 67-69h) and below the absolute temperature limit (registers 6a-6ch) the speed of a fan assigned to that zone is determined as follows: when the temperature reaches the fan temp limit for a zone, the pwm output assign ed to that zone is at fan pwm minimum. between fan temp limit and (fan temp limit + range), the pwm duty cycle increases linearly according to the temperature as shown in the figure below. temperature below fan temp limit: fan is off or at fan pwm minimum depending on bit[7:5] of register 62h and bit 2 of register 7fh temperature limit: pwm output at min fan speed limit+ range: pwm output at 100% duty pwm duty is linear over this range figure 8.1 - fan activity above fan temp limit
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 54 rev. 09-09-04 datasheet example for pwm1 assigned to zone 1: zone 1 fan temp limit (register 67h) is set to 50 c (32h). range (register 5fh) is set to 8 c (7h) fan1 pwm minimum (register 64h) is set to 50% (80h) in this case, the pwm1 duty cycle will be 50% at 50 c . since ( zone 1 fan temp limit ) + ( fan 1 range ) = 50 c + 8 c = 58 c , the fan will run at 100% duty cycle when the temperature of t he zone 1 sensor is at at 58 c. since the midpoint of t he fan control range is 54 c, and the median duty cycle is 75% (halfway between the pwm minimum and 100%), pwm1 duty cycle would be 75% at 54 c. above ( zone 1 fan temp limit ) + ( fan 1 range ), the duty cycle must be 100%. the pwm frequency bits [2:0] determi ne the pwm frequency for the fan. table 8.8 - register setting vs. pwm frequency pwm frequency selection (default =011=29.3hz) freq[2:0] pwm frequency 000 11.0 hz 001 14.6 hz 010 21.9 hz 011 29.3 hz 100 35.2 hz 101 44.0 hz 110 58.6 hz 111 87.7 hz table 8.9 - register setting vs. temperature range range selection (default =1100=32 c) ran[3:0] range ( c) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 1101 40 1110 53.33 1111 80
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 55 rev. 09-09-04 datasheet the range numbers will be used to calculate the slope of the pwm ramp up. for the fractional entries, the pwm will go on full when the temp reaches the next integer value e.g., for 3.33, pwm will be full on at (min temp + 4). 8.20 register 62h, 63h: min/off, spike smoothing register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 62h r/w min/off, zone 1 spike smoothing off3 off2 off1 res zn1e zn1-2 zn1-1 zn1-0 00h 63h r/w zone 2, zone 3 spike smoothing zn2e zn2-2 zn2-1 zn2-0 zn3e zn3-2 zn3-1 zn3-0 00h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. the off/min bits [7:5] specify whether the duty cycle will be 0% or minimum fan duty when the measured temperature falls below the temperature limit register setting (see table below). off1 applies to fan 1, off2 applies to fan 2, and off3 applies to fan 3. if the remote1 or remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the part. if these spikes ar e not ignored, the cpu fan (if connected to part) may turn on prematurely and produce unpleasant noise. fo r this reason, any zone that is connected to a chipset or processor should have spike smoothing enabled. when spike smoothing is enabled, the temperature readi ng registers still reflect the current value of the temperature ? not the ?smoothed out? value. zn1e, zn2e, and zn3e enable temperature smoot hing for zones 1, 2, and 3 respectively. zn1-2, zn1-1, and zn1-0 control smoothing time for zone 1 zn2-2, zn2-1, and zn2-0 control smoothing time for zone 2 zn3-2, zn3-1, and zn3-0 control smoothing time for zone 3 temperature spike with spike smoothing disabled spike 'smoothed' with spike smoothing enabled figure 8.2 - what EMC6D100/emc6d101 sees with and without spike smoothing
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 56 rev. 09-09-04 datasheet table 8.10 - spike smoothing znx-[2:0] spike smoothed over (sec) 000 35 001 17.6 010 11.8 011 7.0 100 4.4 101 3.0 110 1.6 111 0.8 table 8.11 - pwm output below limit depending on value of off/min off/min pwm action 0 at 0% duty below limit 1 at min pwm duty below limit 8.21 registers 64-66h: minimum pwm duty cycle register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 64h r/w fan1 pwm minimum 7 6 5 4 3 2 1 0 80h 65h r/w fan2 pwm minimum 7 6 5 4 3 2 1 0 80h 66h r/w fan3 pwm minimum 7 6 5 4 3 2 1 0 80h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. these registers specify the minimum duty cycle that the pwm will output when the measured temperature reaches the temperature li mit register setting. table 8.12 - pwm duty vs. register setting minimum pwm duty value (decimal) value (hex) 0% 0 00h ? ? ? 25% 64 40h ? ? ? 50% 128 80h ? ? ? 100% 255 ffh
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 57 rev. 09-09-04 datasheet 8.22 registers 67-69h: temperature limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 67h r/w zone 1 fan temp limit 7 6 5 4 3 2 1 0 5ah 68h r/w zone 2 fan temp limit 7 6 5 4 3 2 1 0 5ah 69h r/w zone 3 fan temp limit 7 6 5 4 3 2 1 0 5ah these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. these are the temperature limits for the individual zones. when the current temperature equals this limit, the fan will be turned on if it is not already. when the temperature exc eeds this limit, the fan speed will be increased according to the auto fan algorithm based on the setting in the zone x range / fanx frequency register. default = 90 c=5ah table 8.13 - temperature limit vs. register setting limit limit (dec) limit (hex) -127 c -127 81h ? ? ? -50 c -50 ceh ? ? ? 0 c 0 00h ? ? ? 50 c 50 32h ? ? ? 127 c 127 7fh 8.23 registers 6a-6ch: absolute temperature limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64h 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64h 6ch r/w zone 3 temp absolute limit 7 6 5 4 3 2 1 0 64h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. in auto fan mode, if any zone exceeds the temperatur e set in the absolute limit register, all pwm outputs will increase their duty cycle to 100% except those that are disabled via the f an configuration registers. this is a safety feature that attempts to cool the syst em if there is a potentially catastrophic thermal event.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 58 rev. 09-09-04 datasheet if an absolute limit register set to 80h (-128 c), the safety feature is disabled for the associated zone. that is, if 80h is written into the zone x temp absolute li mit register, then regardless of the reading register for the zone, the fans will not turn on-full based on the absolute temp condition. default =100 c=64h. when any fan is in auto fan mode, then if the temperat ure in any zone exceeds absolute limit, all fans go to full, including any in manual mode, except those that are disabled. therefore, even if a zone is not associated with a fan, if that zone exceeds absolute, then all fans go to full. in this case, the absolute limit can be chosen to be 7fh for those zones that are not as sociated with a fan, so that the fans won't turn on unless the temperature hits 127 degrees. table 8.14 - absolute limit vs. register setting absolute limit abs limit (dec) abs limit (hex) -127 c -127 81h ? ? ? -50 c -50 ceh ? ? ? 0 c 0 00h ? ? ? 50 c 50 32h ? ? ? 127 c 127 7fh 8.24 registers 6d-6eh: zone hysteresis registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 6dh r/w zone 1, zone 2 hysteresis h1-3 h1-2 h1-1 h1-0 h2-3 h2-2 h2-1 h2-0 44h 6eh r/w zone 3, hysteresis h3-3 h3-2 h3-1 h3-0 res res res res 40h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. if the temperature is above fan temp limit, then dr ops below fan temp limit, the following will occur: the fan will remain on, at fan pwm minimum, unt il the temperature goes a certain amount below fan temp limit. that is, when the temperature is less than the temperature limit minus the hysteresis value, the fan will turn off. the hysteresis registers control this amount. see below table for details.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 59 rev. 09-09-04 datasheet table 8.15 - hysteresis settings setting hysteresis 0h 0 c ? ? 5h 5 c ? ? fh 15 c 8.25 register 6f: xor test register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 6fh r/w xor test register res res res res res res res xen 00h this register becomes read only when the lock bit is set. any further attempts to wr ite to this register shall have no effect. the part incorporates an xor tree test mode. when the test mode is enabled by setting the ?xen? bit high via smbus, the part enters xor test mode. the following signals are included in the xor test tree: ? vid0, vid1, vid2, vid3, vid4 ? tach1, tach2, tach3, tach4 ? pwm2, pwm3, int# since the test mode is xor tree, t he order of the signals in the tree is not important. sda and scl are not included in the test tree. 8.26 register 79h: test mode register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 79h r/w test mode antst2 antst1 antst0 oscsel adcavg extclk digtst adctst 00h this register becomes read only when the lock bit is set. any further attempts to wr ite to this register shall have no effect. this register contains the following bits: bit[0] selects the adc test mode. the default for this bit is zero, which deactivates adc test mode. bit[1] selects the digital test mode. the default for this bit is zero, which deactivates digital test mode.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 60 rev. 09-09-04 datasheet bit[2] selects the external clock test mode. the default for th is bit is zero, which deactivates external oscillator clock test mode. bit[3] selects either 8 or 1 averaging for the adc test m ode. the default for this bit is zero, which sets the averaging to 8 for the adc test mode. a one in this bit selects no averaging. bit[4] selects the oscillator clock to be muxed out on the vi d2 pin. the default for this bit is zero, which deactivates mux oscillator clock test mode. bits[7:5] are used by the analog block for test purposes. these three bits of register 4ah are muxed out on pins dig_test_an_pad[2:0]. these bits are also used to mux out either the sdata line or the sclk line to the vid3 pin. if bits[7:5] are ?001?, then the sdata line is muxed out onto the vid3 pin. if bits[7:5] are ?010?, then the sclk line is mux ed out onto the vid3 pin. 8.27 register 7ah: error debug register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7ah r error debug res ara stop invadd rcv rowr invrw nonac 00h this register contains the following bits: bit[0] indicates that no nack was generated by the host during either a read byte protocol or a receive byte protocol. bit[1] indicates a read or a write was attemp ted to an invalid register location. bit[2] indicates a write to a read only register was attempted bit[3 indicates a receive byte protocol was attempted w hen the address pointer register pointed to the 00h location. this is the default regist er location on power on reset. as noted in the ?bus protocols? section of the ?hardware monitoring interface? section, the inter nal address register should be set up with a valid address location by either a send byte protocol or a write byte protocol after power-on-reset, before the receive byte protocol. bit[4] indicates an invalid slave address was detected.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 61 rev. 09-09-04 datasheet bit[5] indicates a premature stop was detected. bit[6] indicates an error was detected during the smbus receive byte protocol response to an ara. bit[7] reserved. 8.28 register 7bh: test digital value register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7bh r/w test digital value 7 6 5 4 3 2 1 0 00h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. 8.29 register 7ch: special function register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7ch r/w special function d2en d1en avg offcfg volten inten monmd lpmd e0h this register becomes read only when the lock bit is set. any further attempts to wr ite to this register shall have no effect. this register contains the following bits: bit[0] low-power mode select 0= sleep mode (default) 1= shutdown mode bit[1] monitoring mode select 0= continuous monitor mode (default) 1= cycle monitor mode bit[2] nint enable (EMC6D100 only)
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 62 rev. 09-09-04 datasheet 0=disables nint pin output function (default) 1=enables nint pin output function bit[3] nint voltage enable (EMC6D100 only) 0=out-of-limit voltages do not affect the state of the ni nt pin (default) 1=enable out-of-limit voltages to make the nint pin active low bit [4] offset register configure 0= offset register configured to the external temperature channel. (default) 1= offset register configured to the internal temperature channel. bit[5] number of measurements of each temp erature and voltage reading made. 0= take 128 separate measurements of the data from the analog block for both remote diode temperature readings before averaging the result and storing it in the value register for remote diode temperature measurements; take 8 separate meas urements of all other voltage and internal temperature readings before averaging. 1 =use 16 averaging for both remote diode temperatur e readings and no averaging for all other voltage and internal temperature values. setting this bit to ?1? would be used for power saving. (default) bit[6] enable interrupt status register status bit to indi cate remote diode 1 thermal error alarm and fault. 0=disable 1=enable (default) bit[7] enable interrupt status register status bit to indi cate remote diode 2 thermal error alarm and fault. 0=disable 1=enable (default). 8.30 register 7eh: interrupt enable register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7eh r/w interrupt enable vcc 12v 5v 33v vcc p 25v 18v 15v ech these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. this register is used to enable the voltage events to se t the corresponding status bits in the interrupt status registers. this register contains the following bits:
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 63 rev. 09-09-04 datasheet bit[0] 1.5v event enable (EMC6D100 only) bit[1] 1.8v event enable (EMC6D100 only) bit[2] 2.5v event enable bit[3] vccp event enable bit[4] 3.3v event enable (EMC6D100 only) bit[5] 5v event enable bit[6] 12v event enable bit[7] vcc event enable these bits are defined as follows: 0=disable 1=enable. see the figure in the ?interrupt status registers? section. 8.31 register 7fh: configuration register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7fh r/w configuration init fttst res suren trdy res int res 10h these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. this register contains the following bits: bit[1] int# pin enable: 0=int# disabled, 1=int# enabled (EMC6D100 only)
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 64 rev. 09-09-04 datasheet bit[2] reserved bit[3] trdy: temperature reading ready. this bit indicate s that the temperature r eading registers have valid values. this bit is used after writing the start bit to ?1?. 0= not valid, 1=valid. bit[4] suren: spin-up reduction enable. this bit enables t he reduction of the spin-up time based on feedback from all fan tachometers associated with each pwm. 0=disable, 1=enable (default) bit[6] fan_tach test mode bit[7] initialization. 8.32 register 80h: fan temp interrupt enable register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 80h r/w fan temp interrupt enable res amb temp fan4 fan3 fan2 fan1 fan 5eh these registers become read only when the lock bit is se t. any further attempts to write to these registers shall have no effect. this register is used to enable t he fan events and the ambien t temperature to set the corresponding status bits in the interrupt status registers. it also contains the fan enable bit to enable fan events to the int# pin and the temp enable bit that enables temperature events to the int# pin. this register contains the following bits: bit[0] fan interrupt enable bit[1] fan 1 event enable bit[2] fan 2 event enable bit[3] fan 3 event enable
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 65 rev. 09-09-04 datasheet bit[4] fan4 event enable bit[5] temp interrupt enable bit[6] ambient event enable bit[7] reserved these bits are defined as follows: 0=disable 1=enable. see the figure in the ?interrupt status registers? section. 8.33 register 81h: tach_pwm register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 81h r/w fan tach/pwm interrupt select t4h t4l t3h t3l t2h t2l t1h t1l a4h these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this register is used to associate a pwm with a tachom eter input. this association is used by the fan logic to determine when to prevent a bit from being set in the interrupt status registers. the fan tachometer will not cause a bit to be set in the interrupt status register: a) if the current value in current pwm duty registers is 00h or b) if the fan is disabled via th e fan configuration register. note: a bit will never be set in the interrupt status for a fan if its tachometer minimum is set to ffffh. see bit definition below. bits[1:0] tach1. these bits determine the pwm associated with this tach. see bit combinations below. bits[3:2] tach2. these bits determine the pwm associated with this tach. see bit combinations below. bits[5:4] tach3. these bits determine the pwm associated with this tach. see bit combinations below. bits[7:6] tach4. these bits determine the pwm associated with this tach. see bit combinations below.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 66 rev. 09-09-04 datasheet bits[1:0], bits[3:2], bits[5:4], bits[7:6] pwm associated with tachx 00 pwm1 01 pwm2 10 pwm3 11 reserved 8.34 register 83h: sync pulse configuration register: on/off register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 83h r/w sync pulse on/off res res res on res res res res 62h this register becomes read only when the lock bit is set. any further attempts to wr ite to this register shall have no effect. 8.34.1 bit [4] on bit [4] of the sync pulse on/off register controls wh ether the synchronization pulse is on or off (active low). the default is on. 8.35 registers 86-88h: smooth temperature reading registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 86h r smooth remote diode reading 1 7 6 5 4 3 2 1 0 n/a 87h r smooth ambient reading 7 6 5 4 3 2 1 0 n/a 88h r smooth remote diode reading 2 7 6 5 4 3 2 1 0 n/a the smooth temperature reading regist ers reflect the smoothed temperatur es of the internal and remote diodes. smoothed temperatures are represented as 8 bi t, 2?s complement, signed numbers in celsius, as shown in table 8.2 - temperature vs. register reading. these registers are read only ? a write to these registers has no effect. these registers hold appropriate values whether smoothing is enabled or not.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 67 rev. 09-09-04 datasheet 8.36 register 89h: adc2 lsb test register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 89h r adc 2 lsb test 7 6 5 4 3 2 1 0 n/a 8.37 registers 8a-8dh: input test register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8ah r input test reg 1 res 6 5 4 3 2 1 0 4dh 8.38 registers 8e-91h: output test register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8bh r/w output test reg 1 7 6 5 4 3 2 1 0 4dh this register becomes read only when the lock bit is set. any further attempts to wr ite to this register shall have no effect. this register must not be written. writing this register may produce unexpected results. 8.39 registers 8a-8dh: input test register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8ch r input test reg 2 res res res 4 3 2 1 0 0eh 8.40 registers 8e-91h: output test register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8dh r/w output test reg 1 res res res 4 3 2 1 0 0eh this register becomes read only when the lock bit is set. any further attempts to wr ite to this register shall have no effect. this register must not be written. writing this register may produce unexpected results.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 68 rev. 09-09-04 datasheet chapter 9 operational description 9.1 maximum guaranteed ratings operating temper ature range .................................................................................................... ............... 0 o c to +70 o c storage temperat ure ra nge ...................................................................................................... ............. -55 o to +150 o c lead temperature range ......................................................................................... refer to jedec spec. j-std-020 maximum v cc ............................................................................................................................... ........................... +5.5v positive voltage on any pin (except for analog inputs), with respect to ground................................................. v cc +0.3v negative voltage on any pin (except for analog inputs), with respect to ground ................................................. ... -0.3v note : stresses above those listed could cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. 9.2 ratings for operation t a = 0 0 c - 70 0 c, vcc=+3.3v 10% parameter symbol min typ max units comments v cc supply current active mode sleep mode shutdown mode i cc i cc i cc 3 500 3 ma a a all outputs open, all inputs transitioning from/to 0v to/from 3.3v. temperature-to-digital converter characteristics internal temperature accuracy external diode sensor accuracy remote source current high level low level -3 -2 -5 -3 1 1 90 5.5 +3 +2 +5 +3 130 7.5 o c o c o c o c o c o c a a 0 0 c <= t a <= 70 0 c 40 0 c <= t a <= 70 0 c resolution -40 0 c <= t s <= 125 0 c 40 0 c <= t s <= 100 0 c resolution
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 69 rev. 09-09-04 datasheet parameter symbol min typ max units comments analog-to-digital converter characteristics total unadjusted error differential non-linearity power supply sensitivity total monitoring cycle time (cycle mode) conversion time (continuous mode) option 1 option 2 input resistance adc resolution tue dnl pss t c(cycle) t c(cts) t c(cts) 1 1 1.0 624 78 140 2 1.4 200 % lsb %/v sec msec msec k ? note 1 note 2 note 3 8 bits input buffer (vid0-vid4,tach1-tach4) low input level high input level v ili v ihi 2.0 0.8 vcc+0.3 v v iod type buffer (scl, sda, pwm1, pwm2, pwm3/address enable, int#) low input level high input level hysteresis low output level v ili v ihi v hys v ol 2.0 500 0.8 vcc+0.3 0.4 v v mv v i ol = +4.0 ma (scl, sda) +8.0 ma (pwm1, pwm2, pwm3/address enable, int#) leakage current (all - digital) input high current input low current digital input capacitance ileak ih ileak il c in 10 -10 10 a a pf (note 4) v in = v cc v in = 0v
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 70 rev. 09-09-04 datasheet notes: ? voltages are measured from the local grou nd potential, unless ot herwise specified. ? typicals are at ta=25c and repres ent most likely parametric norm. ? the maximum allowable power dissipation at any temperature is pd = (tjmax - ta) / qja. ? timing specifications are tested at the ttl logic levels, vil=0.4v for a falling edge and vih=2.4v for a rising edge. tri-state output voltage is forced to 1.4v. note 1: tue (total unadjusted error) includes offse t, gain and linearity errors of the adc. note 2: total monitoring cycle time includes all temperature conversions, all analog input voltage conversions. note 3: the cycle time for option 1 is 624 ms (typical) if 128 measurement s are averaged for the remote diode temperature reading and 8 measurements are av eraged for all voltage and the internal temperature reading. it is 78 ms (typical) for option 2 if 16 measurements are averaged for the remote diode temperature reading and a single measurement is tak en for all voltage and the internal temperature reading (i.e., no averaging). note 4: all leakage currents are measured with all pins in high impedance.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 71 rev. 09-09-04 datasheet chapter 10 timing diagrams 10.1 pwm outputs the following sections show the ti ming for the pwm[1:3] outputs. 10.1.1 with synchronization t1 t2 fanx t3 t4 figure 10.1 - pwmx outp ut timing, sync_msk=0 10.1.2 without synchronization t1 t2 fanx figure 10.2 - pwmx outp ut timing, sync_msk=1 table 10.1 - timing for pwm[1:3] outputs name description min typ max units t1 pwm period (note 1) 11.4 90.9 msec t2 pwm high time (note 2) 0 99.6 % t3 sync pulse period 711.11 usec t4 sync pulse high time 44.44 usec note 1: this value is programmable by the pwm fr equency bits located in the frfx registers note 2: the pwm high time is based on a percentage of the total pwm period (min=0/256*t pwm , max =255/256*t pwm ). during spin-up the pwm high time can reach a 100% or full on. (t pwm = t1)
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 72 rev. 09-09-04 datasheet 10.2 smbus interface p t buf t r t hd;sta p s s t hd;sta t low t hd;dat t high t f t su;dat t su;sta t su;sto sclk sda figure 10.3 ? smbus timing limits symbol parameter min max units comments f smb smb operating frequency 10 400 khz note 1 t sp spike suppression 50 ns note 2 t buf bus free time between stop and start condition 1.3 s t hd : sta hold time after (repeated) start condition. after this period, the first clock is generated. 0.6 s t su : sta repeated start condition setup time 0.6 s t su : sto stop condition setup time 0.6 s t hd : dat data hold time 0.3 0.9 s t su : dat data setup time 100 ns note 3 t low clock low period 1.3 s t high clock high period 0.6 s t f clock/data fall time 20+0.1c b 300 ns t r clock/data rise time 20+0.1c b 300 ns c b capacitive load for each bus line 400 pf note 1: the smbus timing (e.g., max clock frequency of 40 0khz) specified exceeds that specified in the system management bus specificati on, rev 1.1. this corresponds to the maximum clock frequency for fast mode devices on the i 2 c bus. see ?the i 2 c bus specification,? vers ion 2.0, dec. 1998. note 2: at 400khz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter. note 3: if using 100 khz clock frequency, the next data bit output to the sda line will be 1250 ns (1000 ns (t r max) + 250 ns (t su : dat min) @ 100 khz) before the sclk line is released.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 73 rev. 09-09-04 datasheet chapter 11 package outlines 11.1 24 pin ssop package outline, 0.150? wide body, 0.025? pitch min nominal max remarks a 0.053 ~ 0.069 overall package height a1 0.004 ~ 0.010 standoff a2 ~ ~ 0.061 body thickness d 0.337 ~ 0.344 x body size e 0.228 ~ 0.244 y span e1 0.150 ~ 0.157 y body size h 0.007 ~ 0.010 lead frame thickness l 0.016 0.025 0.050 lea d foot length e 0.025 basic lead pitch 0 o ~ 8 o lead foot angle w 0.008 0.010 0.012 lead width ccc ~ ~ 0.004 coplanarity notes: 1 controlling unit: inch. 2 tolerance on the true position of the leads is 0.0035 inches maximum. 3 package body dimensions d and e1 do not include the mold protrusion. maximum mold protrusion is 0.006 inches for ends, and 0.010 inches for sides. 4 dimension for foot length l measured at the gauge plane 0.010 inches above the seating plane. 5 details of pin 1 identifier are optional but must be located within the zone indicated.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 74 rev. 09-09-04 datasheet 11.2 28 pin ssop package outline, 0.150? wide body, 0.025? pitch min nominal max remarks a 0.053 ~ 0.069 overall package height a1 0.004 ~ 0.010 standoff a2 ~ ~ 0.061 body thickness d 0.386 ~ 0.394 x body size e 0.228 ~ 0.244 y span e1 0.150 ~ 0.157 y body size h 0.007 ~ 0.010 lead frame thickness l 0.016 0.025 0.050 lea d foot length e 0.025 basic lead pitch 0 o ~ 8 o lead foot angle w 0.008 0.010 0.012 lead width ccc ~ ~ 0.004 coplanarity notes: 1 controlling unit: inch. 2 tolerance on the true position of the leads is 0.0035 inches maximum. 3 package body dimensions d and e1 do not include the mold protrusion. maximum mold protrusion is 0.006 inches for ends, and 0.010 inches for sides. 4 dimension for foot length l measured at the gauge plane 0.010 inches above the seating plane. 5 details of pin 1 identifier are optional but must be located within the zone indicated.
environmental monitoring and control device datasheet smsc EMC6D100/emc6d101 page 75 rev. 09-09-04 datasheet chapter 12 appendix b ? adc voltage conversion table 12.1 ? analog-to-digital voltage conversions for hardware monitoring block input voltage a/d output 12 v in 5 v in v cc /3.3 v in 2.5 v in 1.8 v in 1.5 v in v ccpin decimal binary <0.062 <0.026 <0.0172 <0.013 <0.009 <0.008 <0.012 0 0000 0000 0.062?0.125 0.026?0.052 0.017?0.034 0.013?0.026 0.009-0.019 0.008-0.016 0.012?0.023 1 0000 0001 0.125?0.188 0.052?0.078 0.034?0.052 0.026?0.039 0.019-0.028 0.016-0.023 0.023?0.035 2 0000 0010 0.188?0.250 0.078?0.104 0.052?0.069 0.039?0.052 0.028-0.038 0.023-0.031 0.035?0.047 3 0000 0011 0.250?0.313 0.104?0.130 0.069?0.086 0.052?0.065 0.038-0.047 0.031-0.039 0.047?0.058 4 0000 0100 0.313?0.375 0.130?0.156 0.086?0.103 0.065?0.078 0.047-0.056 0.039-0.047 0.058?0.070 5 0000 0101 0.375?0.438 0.156?0.182 0.103?0.120 0.078?0.091 0.056-0.066 0.047-0.055 0.070?0.082 6 0000 0110 0.438?0.500 0.182?0.208 0.120?0.138 0.091?0.104 0.066-0.075 0.055-0.063 0.082?0.093 7 0000 0111 0.500?0.563 0.208?0.234 0.138?0.155 0.104?0.117 0.075-0.084 0.063-0.070 0.093?0.105 8 0000 1000 ? ? ? ? ? ? ? ? ? 4.000?4.063 1.666?1.692 1.100?1.117 0.833?0.846 0.600-0.609 0.500-0.508 0.749?0.761 64 (1/4 scale) 0100 0000 ? ? ? ? ? ? ? ? ? 8.000?8.063 3.330?3.560 2.200?2.217 1.667?1.680 1.200-1.209 1.000-1.008 1.499?1.511 128 (1/2 scale) 1000 0000 ? ? ? ? ? ? ? ? ? 12.000?12.063 5.000?5.026 3.300?3.317 2.500?2.513 1.800-1.809 1.500-1.508 2.249?2.261 192 (3/4 scale) 1100 0000 ? ? ? ? ? ? ? ? ? 15.312?15.375 6.380?6.406 4.210?4.230 3.190?3.203 2.297-2.306 1.914-1.922 2.869?2.881 245 1111 0101 15.375?15.437 6.406?6.432 4.230?4.245 3.203?3.216 2.306-2.316 1.922-1.930 2.881?2.893 246 1111 0110 15.437?15.500 6.432?6.458 4.245?4.263 3.216?3.229 2.316-2.325 1.930-1.938 2.893?2.905 247 1111 0111 15.500?15.563 6.458?6.484 4.263?4.280 3.229?3.242 2.325-2.334 1.938-1.945 2.905?2.916 248 1111 1000 15.625?15.625 6.484?6.510 4.280?4.300 3.242?3.255 2.334-2.344 1.945-1.953 2.916?2.928 249 1111 1001 15.625?15.688 6.510?6.536 4.300?4.314 3.255?3.268 2.344-2.353 1.953-1.961 2.928?2.940 250 1111 1010 15.688?15.750 6.536?6.562 4.314?4.330 3.268?3.281 2.353-2.363 1.961-1.969 2.940?2.951 251 1111 1011 15.750?15.812 6.562?6.588 4.331?4.348 3.281?3.294 2.363-2.372 1.969-1.977 2.951?2.964 252 1111 1100 15.812?15.875 6.588?6.615 4.348?4.366 3.294?3.307 2.372-2.381 1.977-1.984 2.964?2.975 253 1111 1101 15.875?15.938 6.615?6.640 4.366?4.383 3.307?3.320 2.381-2.391 1.984-1.992 2.975?2.987 254 1111 1110 >15.938 >6.640 >4.383 >3.320 >2.391 >1.992 >2.988 255 1111 1111

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